Hi Ti Folks,
===========================================In many examples in Ti Installation folders ==========================Part A
piece of code in question
PdLinkSetup[i].CpriCwChannel[Ctrl_Cnt]= 0; //set CW sub channel num to pack 0
PeLinkSetup[i].CpriCwChannel[Ctrl_Cnt]= 0; //set CW sub channel num to pack 0
===========================================AIF2 User Guide Table 8-73 and 8-101==============================Part B
bits field name type
1-0 cw_chan READ_WRITE
Description
All possible CPRI CW per hyperframe are mapped to one of four
CPRI CW staging areas. This allow CPRI CW to be split into 4
different streams. (set 0 ~ 3)
what do you mean by staging area and according to here the values to be set is 0 to 3 since there are only 2 bits
===========================================AIF2 User Guide section 9.1.4==============================Part C
for(i=0;i<256;i++)/* cpri cw lut setup. it could be differently setup for DSP0 and DSP1
to split control word BW */
{
PeLinkSetup.CpriCwChannel[i]= 124; /* set cw channel num to 124. four channels
(124 ~ 127) could be assigned for each DSP to transfer control word */
PeLinkSetup.bEnableCpriCw[i]= TRUE;
}
According to this example, the value is 124~127, which doesn't hold any good as only TWO BITS are there for cw channel.
============================================CSL Code========================== Part D
/* PE 256 Control word LUT register setup*/
for(i = 0; i < 256; i++) {
tempReg = CSL_FMK(AIF2_PE_CPRI_CW_LUT_CW_CHAN, pPeConfig->CpriCwChannel[i]) |
CSL_FMK(AIF2_PE_CPRI_CW_LUT_CW_EN, pPeConfig->bEnableCpriCw[i]);
hAif2->regs->G_PE_LKS[linkIndex].PE_CPRI_CW_LUT[i] = tempReg;
}
=============================Discussion & Questions================
Part A says values to be 0 and that is what is set in example. Part B says 0 to 3 According to staging areas [what do you mean by staging area]? Part C says values of 124 to 127. Part D is CSL code. The confusion here is which is correct value, why and when, staging area explanation.
If it has to be set to 124 ~ 127, i am not sure how that 2 bits can hold those 124~127.
Thanks
RC Reddy
