DDR3 PHY Calculation

Avinash,

I am not sure I understand the question.  Also, I looked at the attached spreadsheet and was not certain I understood the columns.  I have attached a length report generated by the PCB layout tool Allegro.  Most PCB layout tools can generate a report like this.  Alternately, all will allow you to query the lengths of nets manually to generate a similar table.  The DQS nets are point-to-point from the DSP to each SDRAM.  You need the routed track length from the DSP to each SDRAM.  The clock nets are routed in a fly-by topology.  You need the routed track length from the DSP to each SDRAM separately.  These are the values that you need to enter into the PHY_CALC spreadsheet.

Tom

8726.Nyq_EVM_Length_Matching_DDR3_20110811.xls

Hi Tom,

How to calculate the bellow values by using the Excel sheet i have attached.

DATA0_WRLVL_INIT_RATIO = 0x5E;
    DATA1_WRLVL_INIT_RATIO = 0x5E;
    DATA2_WRLVL_INIT_RATIO = 0x5E;
    DATA3_WRLVL_INIT_RATIO = 0x51;
    DATA4_WRLVL_INIT_RATIO = 0x38;
    DATA5_WRLVL_INIT_RATIO = 0x3A;
    DATA6_WRLVL_INIT_RATIO = 0x24;
    DATA7_WRLVL_INIT_RATIO = 0x20;
    DATA8_WRLVL_INIT_RATIO = 0x44;

    DATA0_GTLVL_INIT_RATIO = 0xDD;
    DATA1_GTLVL_INIT_RATIO = 0xDD;
    DATA2_GTLVL_INIT_RATIO = 0xBE;
    DATA3_GTLVL_INIT_RATIO = 0xCA;
    DATA4_GTLVL_INIT_RATIO = 0xA9;
    DATA5_GTLVL_INIT_RATIO = 0xA7;
    DATA6_GTLVL_INIT_RATIO = 0x9E;
    DATA7_GTLVL_INIT_RATIO = 0xA1;
    DATA8_GTLVL_INIT_RATIO = 0xBA;

5023.DDR3_PHY.xlsx

Regards ,

Avinash

Avinash,

I already stated that you will need to fill out the PHY_CALC spreadsheet for each of the UDIMM topologies supported in your system and to put a table in your software.  This is no more complicated than for you to embed the equations and then to have a table of lengths.  The spreadsheet is locked intentionally to limit our support requirements.  I will not be providing the equations.

Tom

Hi Tom,

The PHY_CALC spreadsheet requires the value from DQS(0-7), CK(0-7), DQS_ECC,CK_ECC. But In the Excel Sheet i attached consist of DQS(0-7), DQS#(0-7), DDR3_CLKOUTP& DDR3_CLKOUTN four set of clock routed length are there how to calculate the values as required for PHY_CALC spreadsheet.

Regards,

Avinash

Avinash,

I do not understand your question or your spreadsheet.  The inputs to the PHY_CALC spreadsheet are the clock and data strobe lengths from the DSP to each of the SDRAM chips.  (The address, command, and control nets are length matched to the clock nets since they are all routed in a fly-by configuration.  The data mask and data lines are length matched to their respective data strobe signal since they are point to point.)  The full routed length from the BGA ball of the DSP to the pin/ball of the SDRAM must be considered.

Your spreadsheet lengths are confusing to me.  Did you route the clock, address, command, and control nets in a fly-by configuration?  This topology is described in various TI DDR3 documents as well as the JEDEC standard for DDR3.  It appears that you length matched all of the byte lanes to a single value.  This is acceptable but excessive.  You can match them on an individual byte lane basis where a single byte lane consists of 8 data bits, 1 data mask and a data strobe differential pair.

Tom

How to calculate the DQS 0-7 and CLK 0-7 ?

How to calculate CLK 0-7 using 5set of DDR3_CLKOUTP0,DDR3_CLKOUTN0?

How to calculate Delay per inch value for DDR_PHY calculation?

DSP length match values are

DQS0 --> 1745.23 DQS0# --> 1741.28

DQS1 --> 1743.96 DQS1# --> 1744.81

DQS2 --> 1745.89 DQS2# --> 1741.46

DQS3 --> 1747.44 DQS3# --> 1746.15

DQS4 --> 1744.07 DQS4# --> 1745.55

DQS5 --> 1742.83 DQS5# --> 1748.95

DQS6 --> 1750.8 DQS6# --> 1744.03

DQS7 --> 1741.63 DQS7# --> 1747.21

DDR3_CLKOUTP0 --> 5153.94 DDR3_CLKOUTN0 --> 5158.3

DDR3_CLKOUTP0 --> 5160.21 DDR3_CLKOUTN0 --> 5157.94

DDR3_CLKOUTP0 --> 5155.22 DDR3_CLKOUTN0 --> 5152.79

DDR3_CLKOUTP0 --> 5159.16 DDR3_CLKOUTN0 --> 5147.72

DDR3_CLKOUTP0 --> 5156.1 DDR3_CLKOUTN0 --> 5154.23

Avinash,

You should take the average of the data strobe routes (DQS and DQS#) for each byte lane routed enter these into the spreadsheet directly for DQS0 through DQS7.  Are you using a UDIMM on this board or discrete SDRAM?  If using a UDIMM, then you need to also add to it the routed lengths on the UDIMM from its data sheet.

The clock lengths are confusing to me.  We support memory topologies with 1 or 2 clock pairs.  You list 5 different pairs.  What is this?  Can you provide images of your DDR3 layout or at least the netlist of the DDR3 nets showing the connectivity?

Tom

Hi Tom ,

I have attached the Schematic page of the DDR3 with this mail. I have understand the DQS section now. Can you provide the calculation method for clock .

1803.DDR.rar

Regards,

Avinash

Avinash,

Your schematic shows a 72-bit (64-bit plus ECC) single-rank DDR3 DRAM topology using x16 DRAMs.  They should be wired on the board in a fly-by layout.  Therefore the lengths in the PHY_CALC sheet will be the routed lengths from the DSP to each DRAM.  Specifically, you will fill in the following lengths:

CLK0:  U11 to U17

CLK1:  U11 to U17

CLK2:  U11 to U18

CLK3:  U11 to U18

CLK4:  U11 to U19

CLK5:  U11 to U19

CLK6:  U11 to U20

CLK7:  U11 to U20

CLK ECC:  U11 to U16

Tom

Hi Tom ,

we want to find the average of the DDR3_CLKOUTP0 & DDR3_CLKOUTN0 for U11 to U17,U11 to U18,U11 to U19,U11 to U20,U11 to U16 and substitute them in the CLK(0-7). Else we want to take any one of the parameter (DDR3_CLKOUTP0 & DDR3_CLKOUTN0) and substitute them in CLK(0-7).

Regards,

Avinash

Avinash,

The averages of the diff pair routing lengths from the DSP to each of the DRAMs must be used individually like I listed in my last post.

Tom

Hi Tom,

I can't get the term correctly .The Differential Pair routing length means [(DDR3_CLKOUTP0 + DDR3_CLKOUTN0)/2] Am i correct.

Regards,

Avinash

Avinash,

Yes, the value entered into the PHY_CALC spreadsheet for CLK0 would be the routed length from U11 to U17 of DDR3_CLKOUTP0 plus the routed length from U11 to U17 of DDR3_CLKOUTN0 then divided by 2.  This needs to be repeated for all of the routed clock pairs for each byte lane.

Tom

Tom ，

    Can you please tell me how to generate the excel report?I need to use it to check my PCB,thank!

Jian,

You need to create a spreadsheet like the one I attached near the top of this thread that shows that the length matching rules have been met.  This spreadsheet can either be generated by the PCB layout tool or generated by hand by querying the individual routed net lengths.  The spreadsheet contains equations showing the length matching rules are met.  From this you get the clock lengths and the data strobe lengths.  Once you have this you can enter the proper values into the PHY_CALC spreadsheet.  Does this answer your question?

Tom