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DDR3 init coefficient computing issue

tony lee101086
Prodigy 10 points

Hi experts,

As you know, we are using DDR3 UDIMM on our custom board. To initiate the DDR3 memory we actually use the datasheet of the SDRAM/UDIMM and fill the spreadsheet provide by TI to get the value of the initial value of DSP’s registers. However our final goal would be to make this routine automatic on Power-On, like a PC BIOS would do. To do so, we would like to read back the Presence EEPROM of the DDR3/UDIMM module to get the information and then, compute by ourselves the initial register values in function of the kind of DDR3 UDIMM we plugged.

 Even if, we can already successfully read back the presence EEPROM and interprets the value, we are not able, and we don’t understand how to compute some of the register values. To resume, we have no problem to compute:

 -DDR_SDTIM1   (Formula found in spreadsheet/user guide SPRUGV8C)

-DDR_SDTIM2   (Formula found in spreadsheet/user guide SPRUGV8C)

-DDR_SDTIM3   (Formula found in spreadsheet/user guide SPRUGV8C)

-DDR_SDFG      (Formula found in spreadsheet/user guide SPRUGV8C)

 However, no information found on how to compute:

 -DATA[0..8]_WRLVL_INIT_RATIO

-DATA[0..8]_GTLVL_INIT_RATIO

 -DDR3_CONFIG_REG_12

 -RD_DQS_SLAVE_RATIO

-WR_DQS_SLAVE_RATIO

-WR_DATA_SLAVE_RATIO

-FIFO_WE_SLAVE_RATIO

 For those values, Excel spreadsheet is locked, and user guide provide no equation.

  Would we have support to get back the needed equations?

Thanks in advance.

  • 0
    TI__Mastermind 46460 points

    Tony,

    Fixed leveling is not applicable for production devices and will definately not work with a UDIMM.  Therefore, the fixed override values RD_DQS_SLAVE_RATIO, WR_DQS_SLAVE_RATIO, WR_DATA_SLAVE_RATIO and FIFO_WE_SLAVE_RATIO will not be used.  The KeyStone DDR3 Initialization Application Report SPRABL2 contains the required writes to DDR3_CONFIG_REG_12 and DDR3_CONFIG_REG_23.  UDIMM applications will not need INVERT_CLKOUT set since they will have a long fly-by routing loop for the clock and associated signals to the first SDRAM.  The use of DDR3_CONFIG_REG_23 is driven by the choice of Partial Automatic Leveling or Full Automatic Leveling.  This leaves you with the DATA[0..8]_WRLVL_INIT_RATIO and DATA[0..8]_GTLVL_INIT_RATIO values.  The JEDEC UDIMM specification contains several standard UDIMM topologies.  These define the track routing lengths.  These routing lengths need to be added to your board routing lengths.  For all the topologies you expect to support, you will need to populate the PHY_CALC spreadsheet and to create a table in your software.  Then after the software reads the SEEPROM, it can select the proper entries in the table for this xxx_INIT_RATIO registers.

    Tom