OMAP-L138 MT46H128M16LFCK-6:A detection 256MB problem

I don't think that this version auto detect mem size. Have you modified the line

#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */

in the file /u-boot<version>/include/configs/da850evm.h to reflect the new memory size?

Hi Rishabh,

If you are using the DSP side as well, the memory is shared and the memory map needs to be adjusted. If you are using DSPLink for DSP and ARM communication, please see:

http://processors.wiki.ti.com/index.php/Changing_DSPLink_Memory_Map

Loc said:

I don't think that this version auto detect mem size. Have you modified the line

#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */

We already change it to 256MB in our board header file da850evm.h

#define PHYS_SDRAM_1_SIZE (256 << 20) /* SDRAM size changed to 256MB */

But it is not effecting anything.

Please correct us if we are going wrong as we can see the dram registers are configured in ubl itself.

We have changed the configuration in SDCR register, earlier its value was - 0x08934832 - new value - 0x08934823.

pagesize - 2048 and banks 4 according to datasheet.

According to our analysis it uses "get_ram_size" function called by "dram_init" function from board.c file.

Can you provide your DDR clock frequency setting and the values programmed into DRPYC1R, SDCR, SDCR2, SDTIMR1, SDTIMR2 and SDRCR registers please?

Best regards,

Adam

We are getting DDR clock = 132 Mhz.

After setting the following values we are able to get DRAM size = 256MB.

DRPYC1R = 0x000000C4,

SDCR = 0x0A034623,

SDTIMR1 = 0x184929CB,

SDTIMR2 = 0x380FC700,

SDRCR = 0x00000406,

SDCR2 = 0x00000000.

Debug is:

ARM Clock : 300000000 Hz

DDR Clock : 132000000 Hz                                                                                
RAM Configuration:                                                                                      
Bank #0: c0000000 256 MiB                                                                               
RAM size: 10000000

But after setting some variables in u-boot our u-boot hangs after some times.

So please correct what may be the reason of hanging of u-boot.

We think that there might be some Clock mis-match due to which it gets hangs.

Hi Rishabh,

I am working with AM1808, and using 128MB mDDR instead of 64MB.

I have configured my timing for 128MB as:

Please let us know the timings for 128MB mDDR with 132MHZ.

DRPYC1R= ?,

SDCR= ?

SDTIMR1= ?

SDTIMR2 =?

SDRCR= ?

SDCR2 = ?

Thanks,

Francis

Hi Francis,

Rest all values are same just we have modified the SDCR value for 256MB to 0x08934823.

But if you want it to be 128MB as before you can change it to 0x08934832.

-Rishabh

Hi Riskabh,

I have configured these timing values in AISgen TI tool and selected DDR under mDDR and configured the settings as above.but it is not working in my case.

Please let us know where i need to modify this SDCR value is it in Device.c under UBL or else.

But in my UBL all registers configured as bit wise, Please find the below timing values:

DDR->SDCR |= 0x00800000; // Set BOOTUNLOCK

// **********************************************************************************************
// Setting based on 512Mb mDDR MT46H32M16LFBF-6 on EVM
// Config DDR timings
DDR->DDRPHYCR = (0x0 << 8) | // Reserved
(0x1 << 7) | // EXT_STRBEN
(0x1 << 6) | // PWRDNEN
(0x0 << 3) | // Reserved
(0x4 << 0); // RL

DDR->SDCR = (DDR->SDCR & 0xF0000000) | // Reserved
(0x1 << 27) | // DDR2TERM1
(0x0 << 26) | // IBANK_POS
(0x1 << 25) | // MSDRAMEN
(0x0 << 24) | // DDRDRIVE1
(0x0 << 23) | // BOOTUNLOCK
(0x0 << 22) | // DDR2DDQS
(0x0 << 21) | // DDR2TERM0
(0x0 << 20) | // DDR2EN
(0x0 << 19) | // DDRDLL_DIS
(0x0 << 18) | // DDRDRIVE0
(0x1 << 17) | // DDREN
(0x1 << 16) | // SDRAMEN
(0x1 << 15) | // TIMUNLOCK
(0x1 << 14) | // NM
(0x0 << 12) | // Reserved
(0x3 << 9) | // CL
(0x0 << 7) | // Reserved
(0x2 << 4) | // IBANK
(0x0 << 3) | // Reserved
(0x2 << 0); // PAGESIZE

// Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
DDR->SDTIMR = (((unsigned int) ((97.5 * freq / 1000) - 0.5)) << 25) | // tRFC
(((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 22) | // tRP
(((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 19) | // tRCD
(((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 16) | // tWR
(((unsigned int) ((42.0 * freq / 1000) - 0.5)) << 11) | // tRAS
(((unsigned int) ((60.0 * freq / 1000) - 0.5)) << 6) | // tRC
(((unsigned int) ((12.0 * freq / 1000) - 0.5)) << 3) | // tRRD
(DDR->SDTIMR & 0x4) | // Reserved
(((unsigned int) ((2.0 * freq / 1000) - 0.5)) << 0); // tWTR

// Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
// tRASMAX is rounded down so subtracting 1
// CAS/CL = 3
DDR->SDTIMR2 = (DDR->SDTIMR2 & 0x80000000) | // Reserved
(((unsigned int) ((70000 / 7812.5) - 1)) << 27) | // tRASMAX [(70us/7.8125us)-1]
(0x0 << 25) | // tXP
(0x0 << 23) | // tODT (Not supported)
(((unsigned int) ((120.0 * freq / 1000) - 0.5)) << 16) | // tXSNR
((200 - 1) << 8) | // tXSRD (200 Cycles)
((1 - 1) << 5) | // tRTP (1 Cycle)
(0x0 << 0); // tCKE

DDR->SDCR &= ~0x00008000; // Clear TIMUNLOCK

DDR->SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply
DDR->SDRCR = (0x1 << 31) | // LPMODEN
(0x1 << 30) | // MCLKSTOPEN
(0x0 << 24) | // Reserved
(0x0 << 23) | // SR_PD
(0x0 << 16) | // Reserved
(((unsigned int) ((7.8125 * freq) + 0.5)) << 0); // RR

If there is any modifications under this device.c file please let us know.

Also i have attached the timing sheet which i followed.Please let us know with your valuable suggestions.

Thanks,

Francis

 8182.mDDR_DDR2_Memory_Controller_Register_Calc_Rev2.zip

Hi Francis,

Yes I have made modification in device.c file of UBL in function device_init().

In that we have modified pagesize value of SDCR register. So please go through the datasheet of your DDR and set value accordingly.

-Rishabh

Hi,

There is problem with I2C in my AM1808. After rectified the I2C, Now I am able to boot my UBL+U-Boot bootloader. I

have changed the mDDR 128MB settings under u-boot(da850evm.c) proper. Now I struck at the kernel phase. uImage

has booted then struck at the kernel Os. What should I do ? How can I resolve this issue.

Please find the bootlog:

---------------------------------------------

Booting with TI UBL
Device OPP (300MHz, 1.2V)

U-Boot 2012.04.01 (Aug 23 2013 - 05:46:42)

I2C: ready
DRAM: 128 MiB
WARNING: Caches not enabled
MMC: davinci: 0
SF: Detected M25P64 with page size 64 KiB, total 8 MiB
In: serial
Out: serial
Err: serial
SF: Detected M25P64 with page size 64 KiB, total 8 MiB
Warning: Invalid MAC address read from SPI flash
Net: No ETH PHY detected!!!
Error: Ethernet init failed!
Board Net Initialization Failed
DaVinci-EMAC
Hit any key to stop autoboot: 0
reading boot.scr

** Unable to read "boot.scr" from mmc 0:1 **
reading uImage

2279944 bytes read
## Booting kernel from Legacy Image at c0700000 ...
Image Name: Linux-2.6.33-rc4
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2279880 Bytes = 2.2 MiB
Load Address: c0008000
Entry Point: c0008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

---------------------------------------------

Thanks,

Francis

Hi Francis,

May be for this you need to debug kernel for this.

As after booting from uboot it transfer control to kernel you can put some print in kernel for that.

Please check your uboot environment also as mmc card print should not be there if you are using spi flash for storing images.

So go through that and check it.

-Rishabh