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Cache Coherence in Multicore Processing

Product Design Medha
Intellectual 430 points
Other Parts Discussed in Thread: SYSBIOS

Hi

I am developing an application on EVM6678 which requires all the 8 cores to update a specific memory location. I tried initially by statically assigning the pointer to that memory location. I observed that the value changed in one core was not updating in the other core.

Later, I tried using the IPC module with Sysbios using ListMP(Shared Memory region 1 in DDR3). The same problem described above was observed again. I even tried the CacheWb with CacheWait to see if there cache coherence was the problem. This too did not have the memory location updating correctly.

Could you please suggest if I am missing anything?

Regards

Srikanth

  • 0
    TI__Mastermind 30825 points

    It is a cache coherency issue.  You not only need to perform WB from the core you modified on, but will need to perform an Invalidate on the cores that need to go access this updated version. 

    You may want to look at the C66x DSP Cached User Guide http://www.ti.com/lit/ug/sprugy8/sprugy8.pdf for more details.  Particularly Table B-2.

    Best Regards,

    Chad