hi:
there is sth wrong when I add the driver of DM9000 to linux os on OMAP-L138board using Digital Video Software Development Kit (DVSDK) 4_03_00_06.
I add the platform device DM9000, and I configed the CE4CFG register.I could read the correct ID of DM9000aep in the func “dm9000_probe” in dm9000.c .But the DM9000 didn't work. So I read the ID in the func "dm9000_init_dm9000" in the dm9000.c .,this time I got the wrong ID 0x00000000. I did a lot of work, but I didn't work out. I could not find why there was the wrong ID in the func "dm9000_init_dm9000" in the dm9000.c, and I read the value of CE4CFG register was 0.
espect your repply, thank you
.The pin link and the code I added under that.
DM9000eap woek on 8-bit mode,and linked like SRAM to the EMIF of AM1808.
The DM9000aep's data-bus(d0~d7) connected to the AM1808's data-bus(d0~d7) pin.
The DM9000aep's iow/ior/reset/int separately connected to the AM1808's EMA_WEn/EMA_OEn/RESETOUTn/GPIO0[8].
The DM9000aep's addr-bus pin(A0) connected to the AM1808's add-bus(A0) pin.
The DM9000aep's chip-selected pin(CS) connected to the AM1808's EMA_CSN_4.
And then I added the code in the board-da830-evm.c like that:
static struct resource dm850evm_dm9000_rsrc[] = {
{
/* addr */
.start = 0x64000000,
.end = 0x64000000,
.flags = IORESOURCE_MEM,
}, {
/* data */
.start = 0x64000004,
.end = 0x64000004,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_IRQ | IRQ_TYPE_EDGE_FALLING /* rising (active high) */,
},
};
static struct dm9000_plat_data dm850evm_dm9000_pdata = {
.flags =( DM9000_PLATF_8BITONLY | IRQ_TYPE_EDGE_FALLING | DM9000_PLATF_NO_EEPROM ),
};
static struct platform_device dm850evm_dm9000 = {
.name = "dm9000",
.id = 0,
.resource = dm850evm_dm9000_rsrc,
.num_resources = ARRAY_SIZE(dm850evm_dm9000_rsrc),
.dev = {
.platform_data = &dm850evm_dm9000_pdata,
},
};
static struct platform_device *dm850_evm_devices[] __initdata = {
&dm850evm_dm9000,
};
And I configed the CE4CFG and the pin in func "da850_evm_init" in board-da850-evm.c like that.
#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
#define DA8XX_AEMIF_CE3CFG_OFFSET 0x14
#define DA8XX_AEMIF_CE4CFG_OFFSET 0x18
#define DA8XX_AEMIF_CE5CFG_OFFSET 0x1c
#define DA8XX_AEMIF_ASIZE_8BIT 0x0
static const short da850_evm_dm9000_pins[] = {
DA850_EMA_BA_1,DA850_EMA_BA_0,
DA850_NEMA_CS_2,DA850_NEMA_CS_3,DA850_NEMA_CS_4,DA850_NEMA_CS_5,
DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_A_0,
-1
};
ret = davinci_cfg_reg_list(da850_evm_dm9000_pins);
if (ret)
pr_warning("da850_evm_init: nand mux setup failed: %d\n", ret);
void __iomem *aemif_addr;
aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) &(~0x3),aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
printk("the addr is 0x%x\n",aemif_addr);
printk("the CE2CFG=%x\n",readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET));
unsigned int value = 0;
value |= (0UL<<31); /* [31] SS=0, Normal Mode enabled. */
value |= (0UL<<30); /* [30] EW=0, Extended wait cycles disabled. */
value |= (1UL<<26); /* [29:26] W_SETUP, 0~0x0F */
value |= (6UL<<20); /* [25:20] W_STROBE, 0~0x3F */
value |= (3UL<<17); /* [19:17] W_HOLD, 0~0x07 */
value |= (1UL<<13); /* [16:13] R_SETUP, 0~0x0F */
value |= (7UL<<7); /* [12:7] R_STROBE, 0~0x3F */
value |= (3UL<<4); /* [6:4] R_HOLD, 0~0x07 */
value |= (3UL<<2); /* [3:2] TA, 0~0x03 */
value |= (0UL<<0); /* [1:0] 0=8bit,1=16bit */
writel( value,aemif_addr + DA8XX_AEMIF_CE4CFG_OFFSET);
writel( value,aemif_addr + DA8XX_AEMIF_CE5CFG_OFFSET);
iounmap(aemif_addr);