Hi,
When debugging interrupt prioritizing, I found some notable difference between OMAP L138’s ARM core and other processors.
When an ISR is entered, the GER global interrupt enable bit in AINTC is not cleared. I tested with interrupts triggered by different sources with different priority (all are of IRQ type, none is of FIQ) and this (GER is still set in ISR) remains true. For other processors the global interrupt is typically cleared in an ISR and re-enabled after exiting the ISR. This seems to be a prominent difference.
But why the design adopted the current (not clearing GER in ISR) approach?
Another question is that NESTMODE seems not really effective. I have two interrupts, one is mapped to channel 5 and another mapped to channel 6. I have tested NESTMODE to 00-NONEST, 01-automatic individual, 02-automatic global, however in none of the cases can either interrupt interrupt the other.
Does this mean I missed something in configuration?
Paul