Hi all,
I've got some custom made boards which have OMAPL-138 on connected to MT46H128M16LFCK-6 IT:A mDDR chips. On approx. 30% of these boards mDDR interface seems to be marginal. They work fine running Linux in low temperature (10C degrees), but start to fail when I heat up slightly DDR chip only. In that situation ARM executing out of mDDR memory throws PREFETCH_ABORT exception due to reading back trash from memory. On that board OMAPL-138 and mDDR chips are located within 10mm one to another. I've reviewed PCB layout and found no problems there.
I found that keeping mDDR cool chip improves situation. The same applies when I increase 1V8 power supply from 1.802V up to 1.860V. I've connected high speed scope to 1V8 power supply and it is quiet enough to be well within voltage range. From my previous life as a ASIC designer I recall that at the beginning of the day DDR PHY has to perform calibration procedure to work out the delays of connections between DDR controller and DDR memory. The outcome of that process are the correct settings of delay lines in DDR PHY to get data sampled in the middle of the eye. I could imagine that if this process didn't go well and the actual delay lines are set to sample close to the eye edge, with temperature this sampling point may drift away to the eye edge. Then one would see corrupted bits.
Can you tell me when DDR PHY is performed in OMAPL-138? Is it the part of bootloader functionality and is called when DDR interface AIS command is executed? How this calibration process works and how can I find out the result?
Best regards,
Adam
