Hi,
Based on the AM335x TRM the McASP functional clock is called "PD_PER_MCASP_FCLK" or "Aux Clock" (Page 3949) and is sourced from the PRCM which is sourced from CLK_M_OSC (which is 24MHz on my customer's board). I am wondering if there is a way to either source the McASP functional clock from an alternative clock source (such as a PLL) or do a fractional divide on the Aux Clock? Pg. 3961 indicates that there _might_ be a mechanism to do a fractional divide: "Both the AUXCLK and System Clock are generated from SYSCLK2 (CLKDIV6 domain)." however CLKDIV6 does not appear to be documented.
The issue is that a 24MHz Aux clock can only produce nonstandard frame rates such as 44.117kHz, 50kHz, etc. since the frame rate is calculated like so:
CLK_M_OSC frequency (24MHz) / number of channels (2 for I2S) / channel size (16 for I2S) / (AHCLKX divider + ACLKX divider, both are integers)
Thanks,
Mark