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AM335x - alternative McASP functional clock source (i.e. not CLK_M_OSC)

Other Parts Discussed in Thread: AM3354

Hi,

Based on the AM335x TRM the McASP functional clock is called "PD_PER_MCASP_FCLK" or "Aux Clock" (Page  3949) and is sourced from the PRCM which is sourced from CLK_M_OSC (which is 24MHz on my customer's board). I am wondering if there is a way to either source the McASP functional clock from an alternative clock source (such as a PLL) or do a fractional divide on the Aux Clock? Pg. 3961 indicates that there _might_ be a mechanism to do a fractional divide: "Both the AUXCLK and System Clock are generated from SYSCLK2 (CLKDIV6 domain)." however CLKDIV6 does not appear to be documented.

The issue is that a 24MHz Aux clock can only produce nonstandard frame rates such as 44.117kHz, 50kHz, etc. since the frame rate is calculated like so:

CLK_M_OSC frequency (24MHz) / number of channels (2 for I2S) / channel size (16 for I2S) / (AHCLKX divider + ACLKX divider, both are integers)

Thanks,

Mark

  • Hi Mark,

    There are no fractional divide on the mcasp functional clock.  The best you can do is 24Mhz/544 = 44.117, and 24MHz/500 = 48KHz with a system clock of 24MHz.  You can optionally bring in an external clock through AHCLKX/R pins.  Unfortunately, there are no other choices for the mcasp functional clock. 

     

    Regards,

    James

     

  • Thanks James!

    Unfortunately 48kHz is not possible since the customer is using I2S format (i.e. divider of 500 would not be achievable). I'll see if a 44.117kHz sample rate is usable otherwise I'll check if CLKOUT2 could be configured to drive a high frequency audio clock.

    Mark

  • HI,

    I need set the sampling rate of 96KHZ using 24MHZ Input clock (CLK_M_OSC) in MCASP0 of AM3354.

    So I need ACLKX as 3.07MHZ, AFSX=96KHZ. I can't generate these exact output clock values of ACLKX and AFSX.

    Kindly suggest the configuration for this.

    Regards,

    R.Mahendra kumar