I want to dynamically change the clock on the C6747 EMIFB to the external SDRAM to slow it down to save power. I am running DSP/BIOS 5.x and an audio application with both code and data in internal and external SDRAM.
I run the sdram clock at 1/3 core speed which is 372/3=124 MHz. I plan to go to around 5 MHz ram clock. I do this by running the following code to be executed from internal memory and internal stack :
HWkey = (Uint32)HWI_disable();
SWI_disable();
TSK_disable();
// put memory into self-refresh mode
entryDDRCTL = REG(SDRFC_REG);
REG(SDRFC_REG) &= ~SR_PD_BIT; // select self-refresh mode
REG(SDRFC_REG) |= LPMODEN_BIT; // enable low-power mode
//Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress
while(PLL0_PLLSTAT & 0x1==1){}
//Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default)
PLL0_PLLDIV5 = 0x8000 | PLLDIV5; // Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required
//Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition
PLL0_PLLCMD |= 0x1;
//Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment)
while(PLL0_PLLSTAT & 0x1==1) { }
// restore SDRAM mode
REG(SDRFC_REG) = entryDDRCTL;
HWI_restore(HWkey); // _restore_interrupts(HWkey);
SWI_enable();
TSK_enable();
Questions
1) I would like to know if this is the correct method.
2) Also when I single step this code it works. Free running it can hang the code in one of the while loops. So do I need some kind of delay before checking some of these registers. Putting a delay before the 2 while loops works but I am not sure why and what the delay should be.
Thanks,
Fawad
