ISP releated interrupt problem

Any suggestion?

Regards,
Geza

The cam_hs and cam_vs lines are controller by the same register: CONTROL_PADCONF_CAM_HS (0x4800210c), so I've dumped out the content of it:

CONTROL_PADCONF_CAM_HS (0x4800210c)  >>  0118 0118        0000000100011000 0000000100011000
That means for both channel:
    muxmode:  000    - cam_hs/cam_vs
    PU/PD:        11       - active pullup enabled
    reserved:    000
    input Enable:    1
    off mode:    00000
    wakeupx:    00

I've also managed to modify the pullups, and mode of these pins, but in ISP muxmode they should generate interrupt called: IRQ0STATUS_HS_VS_IRQ - so there is 1 IRQ for two, which should occure every time, when a level change happens on one of these pins.
In the other hand the whole ISP modul has 1 dedicated interrupt line (24) connected into the the MCU/Linux, where the SW demultiplex which exactly occured.

The problem is still that, cam_HS and cam_VS have the same configuration, but if I trigger VS pin it generate IRQ (/proc/interrupt also count this), but if I trigger HS nothing happens .....

I've started to belive this is HW related error in the MCU ...

Regards,

Geza

Geza,

Are you sure that you have enabled HS interrupt? Have you also checked the raw interrupt status registers? We've solved this similar issue before, but it was ocurring because resizer was enabled. Can you check whether resizer is enabled in your case? 

Hi Renjith,

     First off all, thanks for your reply! This HS_VS_IRQ is enabled in ISP_IRQ0ENABLED register, and status register for it is ISP_IRQ0STATUS (in both cases the 31th bit belongs to this IRQ). Therefore as I understood from the documentation there might be some OR logic in the HW for the 2 inputs, which generate this 1 IRQ. In this case VS pin generates interrupt but HS not .. which shouldnt happen  >> as I get both should work or neither ... thats my problem!

This HS_VS_IRQ is a global ISP interrupt line, not connected directly to an ISP module (like resizer) .. but correct me if I am wrong!
Is ISP_IRQ0STATUS register what you mentioned as raw interrupt status register? .. or something else?

Thanks in advance!
Geza

Geza,

Have you checked the field, ISP_CTRL->SYNC_DETECT? Depending on the configuration here, the HS and VS interrupts are triggered.

Hi Renjith,

    ISP_CTRL: 0x0021c340 which means: SYNC_DETECT: 11  (HS_rising edge & VS_rising edge) ... but as I can see it only modify the active edge of the IRQ!
//by the way I started to rewrite the code to use this bad pin as a GPIO (which works), which generate the interrupt and trigger vdint0 and vdint1 in SW .... but havent succeeded yet//

Regards,
Geza

Geza,

The value is 0x3 in the SYNC_DETECT field, which is configured for VS rising edge. You have to select either 0x0 or 0x1 for this field. Also have you checked the register fields  ISP_IRQ0ENABLE.HS_VS_IRQ == 1/ISP_IRQ0ENABLE.HS_VS_IRQ == 1?

Out of curiosity, why do you need HS interrupt? You've get huge number of interrupts per sec, which will be impossible to handle.

Hi Renjith,

    Thanks for the clarification! - I have thought till now, that this SYNC_DETECT only selects the active edge for the pins, but you are right, it also selects 1 of the 2 lines, which will generate the HS_VS_IRQ. .. yes HS line seems like working now!

The goal of this only to debug the 2 sync line .. because AFIAK these are the base of the VD0 / VD1 IRQs generation, which indicates the the the buffers ready for dequeue (DQBUF)... still working on it ..

Regards,
Geza

Hi Renjith,

     The problem was another hw related bug (on the reset line), so:
Thanks for your help once again!!

Regards,
Geza