DDR3 legnth of Clock , addr and command line compared with length of data and data strobe

The skew maximums and minimums are presented in tables 16 and 17 in SPRABI1A.  Generally the address/command lines for DDR3 are longer then the data lines due to the fly-by routing requirement.  These lines are located between the upper data words and the lower data words to match the pinout specification for the UDIMM connector.  If you look at the routing for a UDIMM you will see that the address/command lines are routed up the center, all the way to one end and then across to the far end.  Since the Keystone devices will support different memory topologies the Invert Clock state was added to compensate for address/command lines that may be shorter then then one or more of the data lanes.  In the Minimum Write Leveling Skew Example table (Table 17) you will see that the skew in ps when Invert Clock is enabled is -385ps for DDR-1333.  This means that the data lines may be 2.138 inches longer then the address/command lines.

You stated that in your second release of the layout the length is the same for address/command and data lines.  Are you referring to the length to the first memory device or all of the memory devices?  Keeping the length the same be adding length to the data lines for devices on the end of the fly-by chain is not needed and may unnecessarily complicate your layout.

Hi Bill Taboada,

I am confused about this question too. And I want to show my understanding about this and ask you help me to confirm whether it is right or not.

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From what I understood, according to this pic below

(1) when the Invert clock out state is disabled and DDR3 runs at 1333MT/s

2.027 inchs < addr/cmd/ctl length - data length < 11.861

(2) when the Invert clock out state is enabled and DDR3 runs at 1333MT/s

-2.138 inchs < addr/cmd/ctl length - data length < 7.694

Am I right?

If it is true, I think this constraint is too generous when the Invert clock out state is enabled!

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In the C6670 EVM board, the layout engineer sets the constraint about the skew between addr/cmd/ctl length and data length showed in the pic below

he set the skew between CLK and DQS from -1500 mil to 750 mil.

And I think he disciplines to himself too much.

Is the constraint related with the given DRAM chips? When the DRAM chips we choose changes, and the constraint changes too?

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Regards,

Feng

OK, I got it.