Hi all,
I am using AISgen to convert executable generated by CodeSourcery_G++_Lite tools package into format which is understand by OMAPL-138 bootloader. AISgen front end allows to set up a lot of DDR controller register, but I don't find anything that sets VTPIO_CTL register. My code doesn't touch any of DDR registers. In SPRUGJ4B on page 64 there is a description of bits D0, D1 and D2 in VTPIO_CTL register, which are responsible for OMAP drive strength.
The questions are:
1) Who is setting VTPIO_CTL register and who is performing DDR IO buffer calibration described in chapter 2.13.1 in SPRUGJ4B document? Bootloader?
2) Who is setting bits D0, D1 and D2 in VTPIO_CTL? What the values of these bits mean?
Best regards,
Adam