Hi, I am doing a project which fulfill two successive transfer between DSP1 and DSP2. After the first transfer is done, the FSYNC module should be reset for the next transfer, but I'm not sure if the following code is right or not:
int i;
if(FsyncRegs->CTL2)
{
/*Halt the timer by programming the FSYNC_CTL2_TIMER_HALT bit in the CTL2 register*/
FsyncRegs->CTL2|= CSL_FSYNC_CTL2_TIMER_HALT_MASK;
/*Clear the FSYNC_CTL2_ARM_TIMER bit of the CTL2 register (disarming)*/
FsyncRegs->CTL2&= (~CSL_FSYNC_CTL2_ARM_TIMER_MASK);
/*Clear the FSY_CTL2_TIMER_HALT bit of the CTL2 register*/
FsyncRegs->CTL2&= (~CSL_FSYNC_CTL2_TIMER_HALT_MASK);
/*Perform any set-up changes to timers and event generators.*/
FsyncRegs->CTL2= CSL_FSYNC_CTL2_RESETVAL;
FsyncRegs->CTL1= CSL_FSYNC_CTL1_RESETVAL;
for(i=0; i<22; i++)
FsyncRegs->EGM_CTRL[i].EGMCTRL= CSL_FSYNC_EGMCTRL_RESETVAL;
for(i=0; i<8; i++)
FsyncRegs->EGC_CTRL[i].EGCCTRL= CSL_FSYNC_EGCCTRL_RESETVAL;
/*Set the FSYNC_CTL2_ARM_TIMER bit of the CTL2 register (arming)*/
FsyncRegs->CTL2|= CSL_FSYNC_CTL2_ARM_TIMER_MASK;
}