L2 Memory ( AM3352 )

If you have NOR flash in the design which processor can address and cache in to L2. You can lock the cache except 1-way (32KB) and use it like fast internal memory. SYS/BIOS has APIs to do cache locking and this feature is demonstrated in industrial sdk for AM335x

Thanks for correcting me Pratheesh. I didn't know this, it's good to learn.

Hi Fabio,

We have tried a couple of different techniques to use L2 cache as RAM, but have not been successful.  On the cortex-A8, the 256K L2 was not designed to be used as RAM.

There are two internal 64K rams on the AM335x, so you can have 128K.

I guess to be accurate there is one 64K and one 63K RAM.  The first 1K of one of the internal RAMs is not available.

To be clear, the NOR approach mentioned will work, my post was just for additional information on attempts to use the L2 without NOR, just using the internal memory.

Dear Jeff,

Tks about your answer. 128K is enough room memory for my application. Is there any document describing how to use these 2 banks of memory ?

Thanks in advance,

Fabio Cervone

Fabio,

Please look at the the: AM335x Technical Reference Manual.  One memory is called "Internal SRAM", it is part of the MPU subsystem and accessible by the Cortex-A8 only. The other memory is a shared memory called OCMC RAM and is on the L3 interface and is accessible by all Masters.

Hello,

yes, it's too late for this post. I need your favor.

here I don't understand why except 1way of L2 cache cannot be locked?  

I've searched Cortex A8 CPU mannuals but comes out no answer.

Best Regards,

jT