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SYSBOOT vesus NOR Boot !!!

Jean Lewis
Prodigy 30 points

Hi all,

When I read the documentation about NOR,  page 4554, you said :

Pin used in XIP_MUX1 mode

or

Pin used in XIP_MUX2 mode

It's correct ? Because I don't see MUX2 for the GPMC_Ax !!!!

Does He have a conflict with the SYSBOOT (NOR configuration) and the  NOR addresses ?

 

Thank you,

Jean

 

  • 0
    TI__Prodigy 270 points

    Hi Jean,

    The table is correct. The pins for XIP_MUX1 and XIP_MUX2 mode differ for signal names A0-A15.

    Also, ensure you're using the latest revision of the manual. The latest revision is SPRUH73F. The table in question is on page 4264.

    Best regards.

  • 0 in reply to Theodore Wolff
    Prodigy 30 points

    Thank you,

    But If I use a NOR, we have a conflict with SYSBOOT[11..8] AND GPMC_A12 .. GPMC_A15 !!! I must tie the GPMC_A12 .. GPMC_A27 to 0 so the SYSBOOT[11..8] must be tie to 0

    SYS_BOOT11             SYS_BOOT10          SYS_BOOT9                 SYS_BOOT8

    GPIO2_17                   GPIO2_16                GPIO2_15                      GPIO2_14     

    ( 0 :                              0  = Non-Muxed)      Dont care                       1 = 16Bits, 0 = 8bits

    GPMC_A15                 GPMC_A14             GPMC_A13                    GPMC_A12

    I must use my NOR in 8bits mode only !!!!

  • 0 in reply to Jean Lewis
    TI__Genius 13505 points

    Jean,

    I just helped another customer with a simmilar issue, so I'll pass on the info to you.

    Section 26.1.7.2.2 of the TRM talks about this:

    External logic is needed to isolate the upper address lines (A12–A27) of the NOR flash from the device pins and drive them low during boot. Once the initial software starts running, it can appropriately configure the pinmux setting for the lines and remove the isolation to allow GPMC to drive all the address lines.