One of our customers has the following questions on the timing of the 8168...Thank you.
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I’m working out some timing / control items in my FPGA interface to the 8168. I need to do variable length burst synchronous writes to the FPGA. I’ve been looking at all of the documentation I have and I have a few questions.
1) Does the write signal act as a command that I have to latch or does it remain active for the entire cycle.
2) How does the bus cycle operate with no wait? My FPGA interfaces will always be ready and will be able to keep up with the GPMC interface at whatever rate it is running at.
3) How is the bus cycle terminated? Is the CE de-asserted? Is the write de-asserted? Does the clock just stop?
I really wish there was a better document explaining the operation and timing of the GPMC like TI had for the C64 and DM642 DSPs. I know it is highly configurable but some basic operations would be nice.
