Hi,
We are using OMAP-L138.
We have interfaced a CPLD and 4-Channel External UART Controller (TL16C754C from TI) on EMIFA.
At every 31.25uS rate GPIO will be toggled to inform EDMA to perform read from a register.
When we enable reading from CPLD at the above rate and reading from UART (Baudrate 9600) we are seeing data bytes being dropped on UART.
The read from UART is a CPU read.
I am in the coarse of finding what is causing this issue and does the bandwidth of EMIFA running at 25MHz will allow this kind of configuration or not.
Please let me know if you have any ideas.
Regards,
GSR