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FIQ latency with am335x and fpu register save

Tim Sander
Prodigy 40 points

I am currently evaluating the am335x family for a new product. I would like to know the worst case FIQ latencys of the a8 core and how long it would take to save the fpu

registers/state into the on core 64k sram (TCM?). Code and data would also reside in this RAM as i suppose this is the fastest memory available for this purpose.

Further it would be nice to know if this 64kb sram block is used by the linux kernel or if this is freely available without any changes.

Thanks

Tim

  • 0
    TI__Guru**** 393215 points
    Hi Tim,
     
    Please be aware that FIQ is only available on secure devices, which are not for general sale. On general purpose devices FIQ does not work.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    Prodigy 40 points

    Huh? The FIQ is mentioned all over the technical reference and in the family overview there is no word on this "feature". Is there more information why the fiq mode is not available. The nice thing of fiq mode is that linux does not disable fiq interrupts so they are the easiest path to low latency interrupts on the application processor. Is there any other way to get an interrupt not switched of by the linux time management?

  • 0 in reply to Tim Sander
    TI__Guru* 87040 points

    Tim, this is an error in the interrupt chapter.  FIQs are not supported on a GP device.  The TRM will be updated to notify users of this unsupported feature.

    Regards,

    James

  • 0 in reply to JJD
    Guru 31670 points

    Tim,

    Which is the interrupt that you are trying to handle with FIQ? It may not be possible to write a full-fledged handler in FIQ handler as you won't be access kernel objects properly. 

  • 0 in reply to Renjith Thomas
    Prodigy 40 points

    Hi Renjith Thomas

    I have to react to an external AD Converter. This is higly timing critical and the jitter on this interrupt line is influences the measurement quality in our case. Please be aware that i am currently evaluating the am335x for a new product and i am not currently in posession of such a microprocessor. So my knowledge comes from using a fiq under linux in a arm1136. I know that the FIQ interrupt is a different CPU context and i am not able to access the linux os domain. That said i only plan to access hardware and memory  from within the fiq. The interaction with linux usermode would be realized by an "hijacked" unused interrupt line or if that is possible with the message passing infrastructure of this processor. Given that the FIQ is not available under the am335x is quite a letdown as i have to find a way to get linux not to mask a specific interrupt line. Which is much more work than just setting the interrupt line to FIQ mode. Which means i would have to modify the interrupt disable and enable codepath deep within the kernel infrastructure. So the crucial question still open for me is the worst time latency in a interrupt and the time needed to save/restore fpu registers. It is fully acceptable for me not to access the linux infrastructure as long as i can keep irq latencies as low as possible.

    Best regards

    Tim

  • 0 in reply to Tim Sander
    Guru 31670 points

    Tim,

    I understood your requirements. As you might be aware, there is an M3 code sitting inside AM335x just to do power management. I don't have much experience here, but still have you explored using this code for handling the interrupt as you don't have to worry much about the linux part.

  • 0 in reply to Renjith Thomas
    Guru 31670 points

    Tim,

    Once you handle the interrupt from M3 you can transfer the data to A8 using another interrupt at leisure.

  • 0 in reply to Renjith Thomas
    Prodigy 40 points

    Yes, but the PRUs are planned to be used for fieldbus usage and further they have no fpu. And i really would like to use the fpu for calculations.

  • 0 in reply to Tim Sander
    Guru 31670 points

    I assume that you'll be reading data from ADC alone. Is there anything needs to be computed and written back to the ADC after read? This may not be a clean way, but can you handle the interrupt immediately by reading the data, and send it to A8 for FPU computation? Might be little dirty method.