Hi
I am using EVM6678. I ported the Notify_multicore example with the platform given in the ipc.examples. This was working fine. But when I tried to change the platform to place data memory in DDR3. Stack and Code memory in MSMC it is not executing fully and behaving erratically like getting stuck, IPC start aborting, one core aborting etc. The platform given in the example places stack, code and data in L2 SRAM. The example was not working even if I change the L2 Cache which is set to 0 in the example platform(L2 Memory is configured as ALL SRAM).
In my actual application, the eight processors will perform independent computations accessing data from independent memory locations. There is one master processor which accesses the outputs of all processors(The outputs will be written in predefined memory locations). To achieve this I declared a shared memory in the DDR3 this region will be accessed by all the processors. While each processor doesnot access the same memory location, their access exclusion(all cores may try to access different memory locations in DDR3 at the same time) is not gaurenteed explicity by my program. I am expecting the shared region or the external memory controller(XMC) will take care of the exclusion. I am esuring cahce coherency explicitly.
My Questions are:
- Is the execution of the notify multicore program dependant on the platform? If yes, in what way?
- Is the mutual exclusion of memory access by different cores gaurenteed by sharedmemory module?
- Is there anything else I am missing in the above approach?
Could you please help.
Srikanth
