Hi,
Because of the formula of “SPRUH77 10.2 Power Consumption Overview” gives dynamic power as proportional to voltage square and to frequency, I then worked on minimizing both voltage and frequency. With regard to frequency there are two approaches:
(1) PSC off, which complete gates the clock to specific modules, reflected in the formula above as frequency -> zero
(2) PLL divide down. This make frequency as low as possible.
Should we apply both at the same time? I guess:
- For modules whose PSC is already gated off, further dividing source PLL would not further reduce the power consumption due to the module.
- For modules whose PSC is not off, for example ARM core, further dividing source PLL could reduce power as according to the v^2*f formula above.
But on the other hand, does PLL divider also require additional power? If true, then I guess a balance need to be struck between the power consumption reduced due to reduced frequency and the power increased due to increased PLL divider? The divider should be essentially an intermediate counter between the PLL signal propagation stages, and I have no idea whether a larger counter period would mean more increased power consumption for the specific PLL module (divider), or vice versa?
I am also curious on SPRUH77 10.10 Deep Sleep Mode, where nothing about PLL dividing is discussed. Does it mean TI has experimented and found that the power consumption reduction due to further divided PLL is minimal, so the writer section "10.10 Deep Sleep Mode" simply overlooked that?
Paul