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GPMC WAIT0 status while boot ROM code

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Hi,

I have one question regarding GPMC WAIT0 status checking while the boot ROM running. Our customer is using AM3874.

As you know, the source code of the boot ROM is not disclosed by TI. So our customer does not know the action of the boot ROM code.

According to the customer's analysis, CPU confirms "WAIT0 pin is not wait"(WAIT0=1) when the boot ROM code is running. But our customer does not know its fact before. Our customer is connecting the ASIC to GPMC, and they use normally "WAIT0=0(wait). So their ASIC did not work at first. Then they changed WAIT =0 to WAIT=1 at only after reset.  Now customer's ASIC is working.

But our customer would like to know why CPU confirms the status of WAIT pin when boot ROM code is ruuning. And they also would like to know how many times does CPU confirm WAITpin stauta in boot ROM code?

Please let  me know.

Best regards,

Michi  

  • 0
    TI__Guru**** 170625 points

    Hi Michi,

    Is your final target to use your system (AM3874 + ASIC) working fine with WAIT0 = 0 ?

    To simulate a programmable internal-wait state, an external wait pin can be monitored to dynamically control external access at the beginning (initial access time) of and during a burst access.

    GPMC access time can be dynamically controlled using an external gpmc_wait pin when the external device access time is not deterministic and cannot be defined and controlled only using the GPMC internal RDACCESSTIME, WRACCESSTIME and PAGEBURSTACCESSTIME wait state generator.

    The polarity of the wait pin is defined through the WAITxPINPOLARITY bit of the GPMC_CONFIG register. A wait pin configured to be active low means that low level on the WAIT signal indicates that the data is not ready and that the data bus is invalid. When WAIT is inactive, data is valid.

    GPMC_STATUS[8] WAIT0STATUS - Is a copy of input pin WAIT0. (Reset value of WAIT0 input pin is sampled at IC reset).

    Take a look in figure 4-7. Fast External Boot, from chapter 4 ROM Code. The step after "Configure and Enable GPMC" is "Wait Monitoring Requested?" Wait pin signal WAIT0 is monitored depending on the MBOOT configuration pins (XIP/ XIP with WAIT).

    Depending on the MBOOT option the GPMC is configured to use the WAIT signal connected on the WAIT0 pin or not. Wait pin polarity is set to stall accessing memory when the WAIT0 pin is low. The wait monitoring is intended to be used with memories which require long time for initialization after reset or need to pause while reading data.

    The ROM code first performs an initial wait for device auto initialization (with 250ms timeout) with polling of the ready information. Then, it needs to identify the NAND type connected to the GPMC interface.

    Regards,

    Pavel