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C66 EVB VCC1V8 power sequencing

Wenjun Huang
Expert 1770 points
Other Parts Discussed in Thread: CDCE62005

I was trying to reference design from the C6678EVB on the power sequencing part.

From the schematic and technical hardware manual, I notice something amiss. You can download http://www.advantech.com/Support/TI-EVM/6678le_download3.aspx.

In the technical hardware manual p53, it mentions that the 1.8V output is unlocked and CDCE62005 is initiated after the VCC1V8 is stable for 5ms. However, in the schematic, the VCC1V8 voltage rail does not have a power good signal. So, how does the FPGA knows that the VCC1V8 is stable? 

  • 0
    TI__Mastermind 30825 points

    Wenjun,

    The EVM is built by a third party, Advantech in this case.  It is developed prior to having actual Silicon, and there are things learned during Silicon bring-up efforts, that go into our guidelines, that may not have been incorporated into the EVM platforms.  While the EVM platforms often are used as a reference design by customers.  They are not built with the intent of being a reference design.  They are built with the intent of allowing customers to evaluate our devices, and perform early development and testing.

    Please follow the HW Design Guidelines when designing boards and not the EVM.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1770 points

    Hi Chad,

    Thanks. I will also be following the design guideline when doing the design. However, the design guidelines did not state the way of implementation, while the EVB did state the way of implementation. I have checked that the EVB way of implementation falls under the design guideline in the power sequence order and since the EVB is working, it is good to reference design. I was wondering if the EVB schematic has error in the sense of not having a PGOOD signal at the VCC1V8. Or is there something I have not understood from the hardware manual.

    Thanks.

  • 0 in reply to Wenjun Huang
    TI__Mastermind 30825 points

    The way of implementation, may be up to your discretion, such as in this case. I haven't looked into it, but it may be that the power module being used, as a known ramp, and that the clocking module will not start until a stable level is being used and thus meets the requirements.  I haven't looked into this.  It's something that you probably should look into if you intend to copy the EVMs implementation.

    That said, how exactly are you stating that the EVM has stated the way of implementation and that it falls under the design guideline for power sequencing?  Is this documented some place that I'm missing?  If so please point me to where it's documented and I'll take a look at it.  It may very well be true, I just have not studied it.

    Please keep in mind that what may be sufficient for evaluation modules, may not always be sufficient for production quantity boards.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1770 points

    I have referred to the technical hardware manual p54-57 (http://wfcache.advantech.com/support/DSPM-8301E_EVM%20(6678)-3.0/TMDSEVM6678L_Technical_Reference_Manual_2V01_0320.pdf) and the order of ramping up the voltage rails CVDD->VCC1V0 (CVDD1) -> VCC1V8 -> VCC1V5 is the same as the power sequence core before IO power sequence. The timing is also kept to 5ms for consistency sake. The power sequence guide in the C66 datasheet is detailed and offers a lot of alternatives. However, it is sometime very hard to comprehend, hence I have preferred to stick with the EVB design, after ensuring that the order and timing is in line with the C66 datasheet. You may want to take a look at the technical hardware manual p54-57 to verify what I say.

    Will keep in mind about the EVB design may not be suitable for production quantity board. Thanks.

  • 0 in reply to Wenjun Huang
    TI__Mastermind 30825 points

    I took a look at the schematics.  There's a PGUCD9222 that comes out of the power supply that's from the VCC1V0 which proceeds the VCC1V8, that's feed into the FPGA.  The FPGA then has a VCC1V8_EN1 that it uses to start the ramp of the 1.8V supply.  There isn't a PGOOD indicator, so the FPGA is apparently providing this.  Normally something like this is a simply load and slew rate calculation and creating a hold off for it to give time to stablize.  I'd make the assumption that the FPGA uses a timer inside to do this.  This would need to be confirmed by Advantech.  

    That said, it really doesn't matter as long as you provide the sufficient hold of timing to ensure it's stabilized prior to having the FPGA put out the VCC1V8_PGOOD.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1770 points

    Thanks. I guess that is the only solution, albeit a bit crude.