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MPUPLL_M2NDIV register setting

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Hi,

I have one question about register setting of AM3874.

According to the TRM of AM3874(sprugz7b)  4.4.3 Clocking Configuration, it is written that ARM DPLL is locked to provide 600MHz for the A8.

Also according to the TRM, MPUPLL_M2NDIV register (offset=58h) is set the value of 50013h by the boot ROM code after reset.

But the result of our customer analysis is different.  They confirmed the MPUPLL_M2NDIV register value is "00000001", not "00050013” when boot ROM code finished. They confirmed this by emulator. And the value "00000001" means M2 field of MPUPLL_M2NDIV register is 0. But according to TRM Table2-31, it is written that M2=0 and M3=0 are invalid setting.  Because the calculation of CLKOUT is the following.

CLKOUT=[M/(N+1)]*CLKINP*[1/M2] 

As you know, M2 is used as the denominator. So M2=0 is invalid.

 So customer thinks the setting of the boot ROM code is wrong.

Does anyone know whether the boot ROM code setting is correct or not? Please advise me.

Best regards,

Michi

  • 0
    TI__Guru**** 170625 points

    Hi Michi,

    From my understanding, when calculating the CLKOUT in the formula above, M2 value is not extracted from the MPUPLL_M2NDIV register, but defined in:

    ti-ezsdk_dm814x-evm_5_04_00_11/board-support/u-boot-2010.06-psp04.04.00.01/arch/arm/include/asm/arch-ti81xx/clocks_ti814x.h

    #define MODENA_M2    1

    The whole path is: lowlevel_init.S (assembler start-up code) -> s_init() -> prcm_init() -> modena_pll_config() -> pll_config(). You can check the source code doing this.

    So, when calculating the ARM clock frequency, M2 is nor 0x0 neither 0x5. M2 is 0x1.

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Guru 10030 points

    Dear Pavel-san,

    Thank you for your support.

    Our customer confirmed the value of M2 is "0" after Boot ROM code was executed, and before the initialization software is runnning.

    And they confirmed M2 is 0 in MPUPLL_M2NDIV register. Customer understand PLL is set in initialization software.

    But customer worrys wheher Boot ROM code configure PLL correctly.  If Boot ROM code can't configure PLL correctly, ARM core is not stable unitl the PLL is reconfigured by software after Boot ROM code finished. Customer worrys about its term. Do you have its information? We don't know the boot ROM code is

    correct or not.

    I appreciate your quick reply.

    Best regards,

    Michi