OMAP 4460 IRQ Enable

A quick correction to 2. above... 

The documentation is not very specific about which registers/bits in the GIC correspond to which interrupt lines.  After further review, I think I should be writing 0x00000400 to 0x4824110C in order to enable the UART3_IRQ.  I have done this and I still have the same problem.  In fact, I have written 0xFFFFFFFF to both 0x48241108 and 0x4824110C just to be sure I was enabling the correct interrupt line and the result is the same - the processor does not vector to the RAM IRQ location at 0x4030D018.

Also, still hoping for some help with my other question about RTS code to set up an IRQ stack.

Thanks,

Errett

Errett,

Which software release are you using?  Have you looked at the code in /kernel/android-3.0/drivers/tty/serial for how the UART interrupts are setup?

Regards,
Gina 

I'm using CCS 5.2.1 but the development that I need to do is without an OS (bare metal).  I can download all the Android stuff and start looking through it if necessary.

Assuming that I can eventually work through my current problem of getting an IRQ event to occur, there is still the matter of modifying the existing RTS code to set up a IRQ stack and link a C function to handle the interrupt.  Any thoughts on this (see my original post)?

Thanks,

Errett 

Errett;

You can check next post

http://e2e.ti.com/support/omap/f/849/p/212292/754188.aspx#754188

Errett,

One other note ...

If the IRQ stack means that you want to get an IRQ on RTS change (only LOW -> HIGH change interrupt is supported), it can be done by setting the IER[6] (RTS_IT)
and check if IIR[5:1]= "1000".  Note that it is the lowest priority interrupt.

Regards,
Gina 

Concerning my initial question, I found the answer in another forum.  Basically, there is an additional register in the GIC (GIC_ICDIPTRn) that needed to be programmed to direct the interrupt to Core0.  I'm posting here in the hopes that it helps someone else with the same problem.

http://forums.arm.com/index.php?/topic/16091-cortex-a9mp-gic-configuration/

Concerning my second question about RTS, this is TI's name for the CCS assembly code that is automatically linked in to a program to execute initializations before main() is entered.  This assembly code may need to set up a stack area for executing the ISR, and will certainly need to save/restore context (push/pop registers to/from the user-mode stack) upon entering/leaving the ISR.  I realize that RTS is also a UART signal (and interrupt condition), but my original question is in the context of the assembly boot code.  Here is my question again (copied from the original post in this thread):

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This is really the first step that I need to get things working.  After this, I will need to modify the default RTS code to set up an IRQ stack.  Any helpful tips on doing this?  I located and extracted the rtssrc.zip file in the CCS 5 installation.  I could iteratively try to include and compile the individual sources one by one (starting with boot.asm), but there has to be a better way. 

I really don't want to be wasting time re-writing assembly.  If something already exists along these lines I would be very happy to use it.  

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Thanks,

Errett

Errett,

I am not aware of anything along these lines that already exists.  I think your best reference is the Linux kernel from the TI Android OMAP4 releases, where you can see how the ISRs are configured.

Regards,
Gina 

Errett,

One other note .... Since your questions are in regards to using the RTS code that comes with CCS, you could also post a query in the CCS E2E forum: http://e2e.ti.com/support/development_tools/code_composer_studio/default.aspx

Regards,
Gina