Clock question for each processor in DM8168

Hello,

The clock rate for each processor can be adjust in the Linux kernel. Have a look here:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

Here is one example for the audio clock:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/197142/711664.aspx

BR,

Pavel

Hi Pavel,

    I use DM8168 and DVRRDK_02.80... After referring your link, I just found that we can only change clock of A8/M3Video without M3VPSS/DSP. Am I right?

static struct omap_clk ti816x_clks[] = {
        CLK(NULL,               "secure_32k_ck",        &secure_32k_ck,         CK_TI816X),
 ...
        CLK(NULL,               "main_pll_clk1_ck",     &main_pll_clk1_ck,      CK_TI816X),
 ...
        CLK(NULL,               "main_pll_clk7_ck",     &main_pll_clk7_ck,      CK_TI816X),
 ...
        CLK(NULL,               "ivahd0_ck",                 &ivahd0_ck,             CK_TI816X),
        CLK(NULL,               "ivahd0_sl2_ick",       &ivahd0_sl2_ick,        CK_TI816X),
 ...

Hello,

I am using EZSDK only, I have no access to DVRRDK. On EZSDK, in clock816x_data.c file DSP is known as GEM, and these are the clocks: gem_ick, gem_vbusp_fck and gem_trc_fck.

Considering the M3VPSS clock, these are only in DVRRDK.

BR,

Pavel

Hello Pavel,

Thanks for your reply. I have following question

1. please help to clarify the mapping between in case of M3VPSS.
   Do you have document decribing the relation between clock816x_data.c and the processor?

2. By your speaking and the architecture of SW, it seems impossible to adjust the clock rate.
   Am I right?

Hello Pavel,

Thanks for your reply. I have following question

1. please help to clarify the mapping between in case of M3VPSS.
   Do you have document decribing the relation between clock816x_data.c and the processor?

2. By your speaking and the architecture of SW, it seems impossible to adjust the clock rate dynamically.
   Am I right?