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DDR ram setting issue

jiang lv
Prodigy 110 points

Hi,all

I encountered the display flickering issue. after we investigation, we thought may be the ram speed cause the issue,we use the ti8168 cpu. DDR3 ram.

Our customised card using the speed 621MHZ which is running stable in our board. we setting the DDR configure (which is in file ddr_defs.h) as below

/* For 621 MHz */
#if defined(CONFIG_TI816X_DDR3_621)
#define EMIF_TIM1 0x11135764
#define EMIF_TIM2 0x304a7fe3
#define EMIF_TIM3 0x007F844F
#define EMIF_SDREF 0x100012eb
#define EMIF_SDCFG 0x63c33ab2
//#define EMIF_SDCFG 0x63C33AB2
#define EMIF_PHYCFG 0x0000030e

#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
/* These values are obtained from the CCS app */
#define RD_DQS_GATE 0x129
#define RD_DQS 0x33
#define WR_DQS 0x82
#define RD_DQS 0x3b
#define WR_DQS 0x8e*/
#endif

#endif /* CONFIG_TI816X_DDR3_621 */

when I checked the DDR_PLL setting which is in file clocks_ti816x.h

it only provides 400MHZ,531MHZ,675MHZ,796MHZ, the default setting is 796MHZ as below

/* For 796 MHz */
#if defined(DDR_PLL_796)
#define DDR_N 59
#define DDR_P 0x1
//#define DDR_MDIV1 0x1
#define DDR_MDIV1 0x2  based on data sheet it should be 0x01 why here setting as 0x02?
#define DDR_INTFREQ2 0x8 
#define DDR_FRACFREQ2 0xD99999
#define DDR_MDIV2 0x1E
#define DDR_INTFREQ3 0x8
#define DDR_FRACFREQ3 0x0
#define DDR_MDIV3 0x4
#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
#define DDR_FRACFREQ4 0x0
#define DDR_MDIV4 0x4
#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
#define DDR_FRACFREQ5 0x0
#define DDR_MDIV5 0x4
#endif

can any one help me to tell me how to set these parameter to match 621MHZ which is running in our board ?

  • 0
    Prodigy 110 points

    anyone can help me?

  • 0
    TI__Genius 13460 points

    Is it from the sw leveling GEL? you have missed the part of configuring the frequency...You can find it !

    BTW, the registers should of EMIFs should be correctly set!  you can just follow the value GEL provided.

    Remember to do SW leveling after you re-configure the frequency,,,

     

    Eason

  • 0 in reply to Eason Wang
    Prodigy 110 points

    Eason，

    thanks for your reply.

    Did you mean below parts I can get from GEL?

    DDR_PLL setting which is in file clocks_ti816x.h

    it only provides 400MHZ,531MHZ,675MHZ,796MHZ, the default setting is 796MHZ as below

    /* For 796 MHz */
    #if defined(DDR_PLL_796)
    #define DDR_N 59
    #define DDR_P 0x1
    //#define DDR_MDIV1 0x1
    #define DDR_MDIV1 0x2  based on data sheet it should be 0x01 why here setting as 0x02?
    #define DDR_INTFREQ2 0x8 
    #define DDR_FRACFREQ2 0xD99999
    #define DDR_MDIV2 0x1E
    #define DDR_INTFREQ3 0x8
    #define DDR_FRACFREQ3 0x0
    #define DDR_MDIV3 0x4
    #define DDR_INTFREQ4 0xE /* Expansion DDR clk */
    #define DDR_FRACFREQ4 0x0
    #define DDR_MDIV4 0x4
    #define DDR_INTFREQ5 0xE /* Expansion DDR clk */
    #define DDR_FRACFREQ5 0x0
    #define DDR_MDIV5 0x4
    #endif

  • 0 in reply to jiang lv
    TI__Genius 13460 points

    Yes, you got it.

    Again, remember to set the registers related to frequency and the timing of DDR components.  You can also find these registers of DDR controller and PHY in GEL