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SRIO DSP with FPGA connection problems

Bernd Erbe
Expert 2065 points

Hello,

I'm trying to connect a EVM6678LE (with AMC to PCIe-AdaptorCard) with a FPGA (Stratix II, Altera Wizard SRIO). As example I tested the SRIOdioISR-Example in Loopback-Mode. Configuration is as follows:

-Set PLL to 0x241 (312.5 MHz RefClock, 2.5 GBaud)
-Configure 1 Lane for 1 Port (also tested example with 1 Lane on 4 ports and also 1 4x port, everything worked fine)

For the connection with the FPGA I modified this code-snippets:

-CSL_BootCfgSetSRIOSERDESRxConfig for all ports from Loopback (0x01C404A5) to non-Loopback (0x004404A5)
-CSL_BootCfgSetSRIOSERDESTxConfig for all ports from Loopback (0x007807A5) to non-Loopback (0x001807A5)
-CSL_SRIO_SetNormalMode instead of CSL_SRIO_SetLoopbackMode

Behaviour is as follows:

1) Power up FPGA and DSP the FPGA says PORT_OK; DSP says PORT_NOT_OK; Register Lane_0_status is 0x4F08 (no Rx_sync and Rx_Rdy) instead of 0x7F08 for the loopback-example
2) I also wonder about when I test the loopback-example and change the SERDES-config from loopback to Non-Loopback, that this change has no effect -> example also works...
3) Leaving the DSP in loopback-mode, the FPGA don't get a PORT_OK as I've expected
4) Moreover if I halt the DSP before setting the bootComplete, FPGA also don't have a connection. Running further, FPGA can establish a connection. So it seems everything's alright on FPGA-side, but not on DSP-side

Can somebody give advice how I can debug why the C6678 don't get a PORT_OK?

Best Regards,
Bernd

  • 0
    TI__Genius 9915 points

    Hi Bernd,

    I am not sure about one thing in your setup, if you use an AMC to PCIe daughter card, how are you conecting your FPGA to EVM through SRIO?

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    Expert 2065 points

    Hello Arun,

    we've an own testboard with an FPGA which is connected electrical with an AMC-Plug. This plug is used to connect with the AMC to PCIe adaptor card. This testboard is just for testing until our own board (where FPGA and DSP are connected directly) arrives.

    If you wanna know more details I've to ask my colleague, he developed this test setup.

    Best Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    TI__Mastermind 18146 points

    Hi Bernd,

    do you see any port errors?

    Kind regards,

    one and zero

  • 0 in reply to one and zero
    Expert 2065 points

    Hello one and zero,

    I've checked all error registers (quite a lot) by saving the memory from address 0x0290b140 for 4076 words. Differences between loopback-Example and connection to FPGA are only in these registers:

    SP0_ACKID_STAT (0xB148): 0x04000404    vs.    0x00000000
    SP0_ERR_STAT    (0xB158): 0x00000002    vs.     0x00000001
    LANE0_STAT0        (0xE010): 0x00007F08    vs.     0x00004F08
    LANE1_STAT0        (0xE030): 0x01004008    vs.     0x01004F08

    Other registers are equal (I also attached the memory dump).

    Regards,
    Bernd

    Memory Dumps.zip
  • 0 in reply to Bernd Erbe
    Expert 2065 points

    Hello one and zero,

    a small update: we've found out that on FPGA side, only a srio initialized is set, but no PORT_OK. So we are going to debug a little bit deeper to check what's the PORT-Status on FPGA side. I'll give an update when we've done this.

    Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    Expert 2065 points

    Hello,

    we've improved a lot of things, but the SRIO-connection doesn't work. So we used a simple AMC Edge Connector and hard wired the pin 91 <-> 88 and 90 <-> 87 (SRIO1). I use the SRIOdioISR-Example (configuration to one port).

    The loopback works, the normal mode in conjunction with the AMC Edge Connector doesn't work (Port not operational). Testing the same with our testboard with the FPGA, it works -> wrong configuration has to be on the DSP-side.

    So I wonder what's the problem or is there an obvious reason why this won't work?

    Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    Expert 2065 points

    Small update:

    -the SRIOdioISR-Example works in that way with the AMC Edge Connector that the Port 0 becomes operational (forgot to set the bit for Host)
    -sending packets failed, but for this I just have to check the device ID's, etc...
    -now only deactivating the Host bit and connecting to the FPGA board, the Port don't become operational

    Maybe the reference clock (PLL) in conjunction with the GB for the ports could be a problem? Our FPGA-Board is not able to be set to 3.125 GB (we don't have a PLL for 160 MHz). I can change the GB for example to 2.5 GB on the EVM, but in the manual and source code (SRIO LLD) I think I've read that the EVM is only able to give 3.125 GB.

    Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    Expert 2065 points

    Hello together,

    after further tests we're standing on this point (and are not able to go further; always use the SRIOdioISR-Example on DSP-side configured to 2.5Gbps):

    -Loopback works
    -Port is operational on EVM with AMC to PCIe Adaptor Card and AMC Edge Connector (hard wired pins as described above); but packet write / read fails (IRQ for TxCompletion is missing)
    -Port is operational on FPGA-Board with AMC Edge Connector

    -Connecting FPGA-Board with DSP-EVM via AMC Edge Connectors, it's not possible to get the ports operational (Port initialized is there, but then Port errors come up -> Register says that link training failed)

    Are there any simple possibilities for further debugging?

    Thanks for help...

    Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    TI__Genius 9915 points

    Hi Bernd,

    There is a gel file to dump all the SRIO registers. The gel file is attached in the post below. Can you dump the registers and see if that helps you?

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/187410.aspx?pi67630=1

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    TI__Mastermind 18146 points

    Hi Bernd,

    could you please try to lower the speed to 1.25GB?

    When the link training fails this could indicate a relatively bad physical connection.

    Kind regards,

    one and zero

  • 0 in reply to one and zero
    Expert 2065 points

    Hello,

    we'll try both recommendations and then give feedback. Due to holiday of my colleagues, this can last some time.

    Regards,
    Bernd

  • 0 in reply to Bernd Erbe
    Expert 2065 points

    Hello,

    we've tried a little bit more and think that we've electrical problems between the two evaluation boards. Therefore we will wait until our own developed board will arrive with the FPGA and DSP being on the same board, having the same clock, power supply and so on.

    Thanks for your advice.
    Regards,
    Bernd