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Can we run A/D & D/A at the same time in ezdsp5535?
Would you also provide information on what software code base, including version, you are using as a baseline?
If you are starting from an example and modifying it, please cite which example.
What behavior are you observing?
From your descriptions above, it seems like you have an ADC hooked up to the I2S1 interface and a DAC hooked up to the I2S2 interface. Based on your description, if you only initialize one of the interfaces (as a test), you observe appropriate, expected behavior of data coming in (ADC case) and data going out (DAC case). But if you initialize both, then whichever was initialized last is the only interface that is operational.
What behavior do you see with the first interface that is initialized and does not work? Is it just inactive? Or are you seeing data movement, but corruption?
Hi Brandon,
you understand my problem.
Attached is the code I am using.
Modified from csl_i2s_DmaExample.
Calling
Setup_I2S_DA();
Setup_I2S_AD();
from main file.
#define I2S_C
#include "I2S.h"
#include "ezdsp5535_gpio.h"
#include "ezdsp5535.h"
#include "ezdsp5535_led.h"
#include <string.h>
#include "tistdtypes.h"
#include "csl_dma.h"
#include "csl_i2s.h"
#include <csl_general.h>
#include <stdio.h>
#include<math.h>
#define CSL_TEST_FAILED (1)
#define CSL_TEST_PASSED (0)
#define CSL_DMA0_CH0 (0)
#define CSL_I2S_DMA_BUF_LEN (4000)
#define DA_BUF_LEN (108)
//CSL_DMA_ChannelObj dmaObj_left;
//CSL_DMA_ChannelObj dmaObj_right;
CSL_DMA_ChannelObj dmaObj;
CSL_DMA_Handle dmaLeftTxHandle;
CSL_DMA_Handle dmaRightTxHandle;
CSL_DMA_Handle dmaLeftRxHandle;
CSL_DMA_Handle dmaRightRxHandle;
CSL_DMA_Config dmaConfig;
#pragma DATA_ALIGN(i2sDmaWriteLeftBuff, 8);
Uint32 i2sDmaWriteLeftBuff[DA_BUF_LEN] = {0xDEADBEEF};
#pragma DATA_ALIGN(i2sDmaWriteRightBuff, 8);
Uint32 i2sDmaWriteRightBuff[DA_BUF_LEN] = {0x12345678};
#pragma DATA_ALIGN(i2sDmaReadLeftBuff, 8);
Uint32 i2sDmaReadLeftBuff[CSL_I2S_DMA_BUF_LEN] = {0x00000000};
#pragma DATA_ALIGN(i2sDmaReadRightBuff, 8);
Uint32 i2sDmaReadRightBuff[CSL_I2S_DMA_BUF_LEN] = {0x00000000};
//
//This is functionality is to configure DMA
//for the source and destination address.
//Function returns:
//CSL_DMA_Handle - Valid handler
//NULL - Invalid handler
//
//CSL_DMA_Handle CSL_configDmaForI2s(CSL_DMAChanNum chanNum, CSL_DMA_ChannelObj *dmaObjPtr)
CSL_DMA_Handle CSL_configDmaForI2s(CSL_DMAChanNum chanNum)
{
CSL_DMA_Handle dmaHandle;
CSL_Status status;
ioport volatile CSL_SysRegs *sysRegs;
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
//enable the corresponding DMA clock from PCGCR Registers//
CSL_FINS(sysRegs->PCGCR2, SYS_PCGCR1_DMA0CG, CSL_SYS_PCGCR1_DMA0CG_ACTIVE);
CSL_FINS(sysRegs->PCGCR2, SYS_PCGCR2_DMA1CG, CSL_SYS_PCGCR2_DMA1CG_ACTIVE);
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR2_DMA2CG, CSL_SYS_PCGCR2_DMA2CG_ACTIVE);
CSL_FINS(sysRegs->PCGCR2, SYS_PCGCR2_DMA3CG, CSL_SYS_PCGCR2_DMA3CG_ACTIVE);
status = DMA_init();
if (status != CSL_SOK)
{
printf("DMA_init() Failed \n");
dmaHandle = NULL;
}
//dmaHandle = DMA_open(chanNum, dmaObjPtr,&status);
dmaHandle = DMA_open(chanNum, &dmaObj,&status);
if (dmaHandle == NULL)
{
printf("DMA_open() Failed \n");
dmaHandle = NULL;
}
status = DMA_config(dmaHandle, &dmaConfig);
if (status != CSL_SOK)
{
printf("DMA_config() Failed \n");
dmaHandle = NULL;
}
return(dmaHandle);
}
/*
//
//This is functionality Transmit and
//receive data with DMA mode.
//The data transmission and receive happen in stereo mode.
//Function returns:
//CSL_TEST_FAILED -Failure
//CSL_TEST_PASSED -Success
//
/******************************************************************************
* D/A
* PORT 2
******************************************************************************/
#define SINE_TABLE_SIZE 108
#define ARRAY_SIZE 216
#define RX_CYCLES 100 // One cycle is one pass through the D/A table
#define DA_OFFSET 0x2aaaaaab // 1 volt DC
#define INIT_SCALE_FACTOR 0x2aaaaaab // 0x26666666 // +/- 0.9V
#define COS_TABLE_MAX 1000
float const cosinetable[SINE_TABLE_SIZE]=
{
1000,116.0929141,-973.0448706,-342.0201433,893.6326403,549.5089781,-766.0444431,
-727.3736416,597.1585917,866.0254038,-396.079766,-957.9895123,173.6481777,998.3081583,
58.14482891,-984.807753,-286.8032327,918.2161069,500,-802.1231928,-686.2416379,
642.7876097,835.4878114,-448.7991802,-939.6926208,230.6158707,993.2383577,-2.44921E-13,
-993.2383577,-230.6158707,939.6926208,448.7991802,-835.4878114,-642.7876097,
686.2416379,802.1231928,-500,-918.2161069,286.8032327,984.807753,-58.14482891,
-998.3081583,-173.6481777,957.9895123,396.079766,-866.0254038,-597.1585917,
727.3736416,766.0444431,-549.5089781,-893.6326403,342.0201433,973.0448706,
-116.0929141,-1000,-116.0929141,973.0448706,342.0201433,-893.6326403,-549.5089781,
766.0444431,727.3736416,-597.1585917,-866.0254038,396.079766,957.9895123,
-173.6481777,-998.3081583,-58.14482891,984.807753,286.8032327,-918.2161069,
-500,802.1231928,686.2416379,-642.7876097,-835.4878114,448.7991802,939.6926208,
-230.6158707,-993.2383577,-6.37066E-12,993.2383577,230.6158707,-939.6926208,
-448.7991802,835.4878114,642.7876097,-686.2416379,-802.1231928,500,918.2161069,-286.8032327,
-984.807753,58.14482891,998.3081583,173.6481777,-957.9895123,-396.079766,866.0254038,
597.1585917,-727.3736416,-766.0444431,549.5089781,893.6326403,-342.0201433,-973.0448706,116.0929141
};
//Port 2
//#define DA_I2S_CHAN I2S_INSTANCE2
void Setup_I2S_DA(void)
{
Int16 status = CSL_TEST_FAILED;
Int16 result;
CSL_I2sHandle hI2s_DA;
I2S_Config hwConfig;
Uint16 looper;
float ftemp,ft1,ft2,ft3,ft4;
Uint32 temp32;
Uint16 temp16;
Uint16 LSW, MSW;
/*status = DMA_init();
if (status != CSL_SOK)
{
printf("DMA_init() Failed \n");
// dmaHandle = NULL;
}
*/
// Initialize data buffers //
for(looper=0; looper < DA_BUF_LEN; looper++)
{
LSW = 0;
ft1 = cosinetable[looper];
ft2 = (INIT_SCALE_FACTOR / COS_TABLE_MAX);
ft3 = ft1 * ft2;
ftemp = ft3 + DA_OFFSET;
temp32 = trunc(ftemp);
//LSW = temp32 & 0xffff;
//MSW = temp32 /0x10000;
//ftemp = looper;
//ftemp = 2*ftemp/108;
//ftemp *= (2*3.14159);
//ftemp = sin(ftemp);
//ftemp *= INIT_SCALE_FACTOR;
//ftemp += DA_OFFSET;
//temp32 = trunc(ftemp);
//temp32 = looper;
//temp32 *= (INIT_SCALE_FACTOR/108);
//temp32 = DA_OFFSET - temp32;
i2sDmaWriteLeftBuff[looper] = temp32;
i2sDmaWriteRightBuff[looper] = temp32; // DA_OFFSET;
} // for looper
//// On C5505/C5515 DSP DMA swaps the words in the source buffer
//before transferring it to the I2S registers. No data mismatch is
//observed When the write and read operations are done in DMA mode
//as the word swap occurs in both the operations.
//There will be data mismatch if data write is in DMA mode
//and read is in polling mode or vice versa.
// To ensure that the data will be written to memory properly in DMA mode
// words in the write buffer are swapped by software. During DMA transfer
// DMA hardware again will do a word swap which will bring the data buffer
// back to original values. Word swap is not required for read
// buffer after read operation in DMA mode as I2S hardware will do
// a word swap on the data before looping it back to receive registers.
// This is peculiar behavior of the I2S HW in loopback mode
//
// Swap words in I2S write buffer //
/* result = DMA_swapWords((Uint16*)i2sDmaWriteLeftBuff, 2*CSL_I2S_DMA_BUF_LEN);
if(result != CSL_SOK)
{
printf ("DMA word swap API failed\n");
status = CSL_TEST_FAILED;
//return (status);
}
*/
// Open the device with instance 2 //
hI2s_DA = I2S_open(I2S_INSTANCE2, DMA_POLLED, I2S_CHAN_STEREO);
if(NULL == hI2s_DA)
{
status = CSL_TEST_FAILED;
//return (status);
}
else
{
printf ("I2S Module Instance opened successfully\n");
}
// Set the value for the configure structure //
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW;
hwConfig.clkPol = I2S_RISING_EDGE;
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_DISABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_32;
hwConfig.i2sMode = I2S_MASTER;
hwConfig.clkDiv = I2S_CLKDIV2;
hwConfig.fsDiv = I2S_FSDIV64;
hwConfig.FError = I2S_FSERROR_DISABLE;
hwConfig.OuError = I2S_OUERROR_DISABLE;
// Configure hardware registers //
result = I2S_setup(hI2s_DA, &hwConfig);
if(result != CSL_SOK)
{
status = CSL_TEST_FAILED;
//return (status);
}
else
{
printf ("I2S Module Configured successfully\n");
}
// Configure DMA channel for I2S write //
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_TX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_DISABLE;
dmaConfig.chanDir = CSL_DMA_WRITE;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = (4*DA_BUF_LEN);
dmaConfig.srcAddr = (Uint32)i2sDmaWriteRightBuff;
dmaConfig.destAddr = (Uint32)(0x2A0C);
//dmaRightTxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN5,&dmaObj_right);
dmaRightTxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN5);
if(dmaRightTxHandle == NULL)
{
printf("DMA Config for I2S Write Failed!\n!");
//return(CSL_TEST_FAILED);
}
I2S_transEnable(hI2s_DA, TRUE);
status = DMA_start(dmaLeftTxHandle);
if(status != CSL_SOK)
{
printf("I2S Dma Write Failed!!\n");
//return(result);
}
//while(DMA_getStatus(dmaLeftTxHandle));
// Configure DMA channel for I2S write //
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_TX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_DISABLE;
dmaConfig.chanDir = CSL_DMA_WRITE;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = (4*DA_BUF_LEN);
dmaConfig.srcAddr = (Uint32)i2sDmaWriteLeftBuff;
dmaConfig.destAddr = (Uint32)(0x2A08);
//dmaLeftTxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN4,&dmaObj_left);
dmaLeftTxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN4);
if(dmaLeftTxHandle == NULL)
{
printf("DMA Config for I2S Write Failed!\n!");
// return(CSL_TEST_FAILED);
}
I2S_transEnable(hI2s_DA, TRUE);
status = DMA_start(dmaRightTxHandle);
if(status != CSL_SOK)
{
printf("I2S Dma Right Write Failed!!\n");
//return(result);
}
status = DMA_start(dmaLeftRxHandle);
if(status != CSL_SOK)
{
printf("I2S Dma Left write Failed!!\n");
// return(result);
}
//while(DMA_getStatus(dmaRightTxHandle));
//I2S_transEnable(hI2s_AD, FALSE);
/** Reset the registers */
//result = I2S_reset(hI2s_AD);
printf("D/A DMA Started.\n");
}
/******************************************************************************
* A/D
* PORT 3 ON REAL HARDWARE
* PORT 1 ON CCS
******************************************************************************/
// Port 3 on real hardware
// Port 1 on CCS
// #define AD_I2S_CHAN I2S_INSTANCE3 // On the target system
//#define AD_I2S_CHAN I2S_INSTANCE1 // On the CCS
void Setup_I2S_AD(void)
{
Int16 status = CSL_TEST_FAILED;
Int16 result;
CSL_I2sHandle hI2s_AD;
I2S_Config hwConfig;
Uint16 looper;
/* status = DMA_init();
if (status != CSL_SOK)
{
printf("DMA_init() Failed \n");
// dmaHandle = NULL;
}*/
// Initialize data buffers //
for(looper=0; looper < CSL_I2S_DMA_BUF_LEN; looper++)
{
//i2sDmaWriteLeftBuff[looper] = 0x12345678;
i2sDmaReadLeftBuff[looper] = 0x55;
i2sDmaReadRightBuff[looper] = 0xaa;
}
//// On C5505/C5515 DSP DMA swaps the words in the source buffer
// before transferring it to the I2S registers. No data mismatch is
// observed When the write and read operations are done in DMA mode
// as the word swap occurs in both the operations.
// There will be data mismatch if data write is in DMA mode
// and read is in polling mode or vice versa.
// To ensure that the data will be written to memory properly in DMA mode
// words in the write buffer are swapped by software. During DMA transfer
/// DMA hardware again will do a word swap which will bring the data buffer
// back to original values. Word swap is not required for read
// buffer after read operation in DMA mode as I2S hardware will do
// a word swap on the data before looping it back to receive registers.
// This is peculiar behavior of the I2S HW in loopback mode
//
// Swap words in I2S write buffer //
/*result = DMA_swapWords((Uint16*)i2sDmaWriteLeftBuff, 2*CSL_I2S_DMA_BUF_LEN);
if(result != CSL_SOK)
{
printf ("DMA word swap API failed\n");
status = CSL_TEST_FAILED;
return (status);
}*/
// Open the device with instance 1 //
hI2s_AD = I2S_open(I2S_INSTANCE1, DMA_POLLED, I2S_CHAN_STEREO);
if(NULL == hI2s_AD)
{
status = CSL_TEST_FAILED;
//return (status);
}
else
{
printf ("I2S Module Instance opened successfully\n");
}
// Set the value for the configure structure //
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW;
hwConfig.clkPol = I2S_RISING_EDGE;
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_DISABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_32;
hwConfig.i2sMode = I2S_SLAVE;
hwConfig.clkDiv = I2S_CLKDIV2;
hwConfig.fsDiv = I2S_FSDIV64;
hwConfig.FError = I2S_FSERROR_DISABLE;
hwConfig.OuError = I2S_OUERROR_DISABLE;
// Configure hardware registers //
result = I2S_setup(hI2s_AD, &hwConfig);
if(result != CSL_SOK)
{
status = CSL_TEST_FAILED;
// return (status);
}
else
{
printf ("I2S Module Configured successfully\n");
}
// Configure DMA channel for I2S Read //
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_DISABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S1_RX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_DISABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = (4*CSL_I2S_DMA_BUF_LEN);
dmaConfig.srcAddr = (Uint32)(0x2928);
dmaConfig.destAddr = (Uint32)i2sDmaReadLeftBuff;
dmaLeftRxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN12);
if(dmaLeftRxHandle == NULL)
{
printf("DMA Config for I2S Read Failed!\n!");
// return(CSL_TEST_FAILED);
}
// I2S_transEnable(hI2s_AD, TRUE);
// status = DMA_start(dmaLeftRxHandle);
//if(status != CSL_SOK)
//{
// printf("I2S Dma Read Failed!!\n");
// return(result);
//}
//while(DMA_getStatus(dmaLeftRxHandle));
// Configure DMA channel for I2S Read //
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_DISABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S1_RX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_DISABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = (4*CSL_I2S_DMA_BUF_LEN);
dmaConfig.srcAddr = (Uint32)(0x292C);
dmaConfig.destAddr = (Uint32)i2sDmaReadRightBuff;
dmaRightRxHandle = CSL_configDmaForI2s(CSL_DMA_CHAN13);
if(dmaRightRxHandle == NULL)
{
printf("DMA Config for I2S Read Failed!\n!");
//return(CSL_TEST_FAILED);
}
I2S_transEnable(hI2s_AD, TRUE);
status = DMA_start(dmaRightRxHandle);
//DMA_start(dmaRightRxHandle);
if(status != CSL_SOK)
{
printf("I2S Dma Read Failed!!\n");
// return(result);
}
status = DMA_start(dmaLeftRxHandle);
if(status != CSL_SOK)
{
printf("I2S Dma Read Failed!!\n");
// return(result);
}
//while(DMA_getStatus(dmaRightRxHandle));
//I2S_transEnable(hI2s_AD, FALSE);
// Reset the registers
//result = I2S_reset(hI2s_AD);
}
That is great news.
When you have an opportunity, it would be nice if you could share what you discovered here to conclude the thread.