PLL setting

Dear Michi-san,

I'm not 100% sure in case of AM3874. But generally you put A8 in bypass clock which, before changing its own clock. So there won't be any issues. 

Dear Renjith-san,

Thank you for your reply.

Please let me know more regarding your reply. Do you mean clock is unstable while changing PLL? So it is needed to enter the bypass mode by setting PONIN=1 and PGOODIN=1 of <MODULE>PLL_PWRCTRL registers. Is my understanding right?

I have one more question. When the AM3874 is in bypass mode, how is frequency? According to the TRM, when AM3874 is in bypass mode, bypass clk = CLKINPULOW(ULOWCLKEN=1) or bypass clk=CLKINP/(N2+1);N2=0 (ULOWCLKEN=0). I know CLKINP=20MHz. But I don't know CLKINPULOW's frequency. Please let me know it.

Best regards,

Michi

Dear Michi-san,

I'm referring to AM3874 TRM section 2.5

AM3874 TRM said:

The DPLLS is a high resolution frequency synthesizer PLL with built in level shifters which allows the generation of frequencies upto 1GHz. DPLLLS has a pre-divide feature which allows the user to divide, for instance, a 20 MHz or 27 MHz reference clock to 1 MHz and then multiply up to 1 GHz maximum frequency. All PLLs come up in bypass mode at reset. SW needs to program all the PLL settings appropriately and then wait for PLL to be locked. Once it is locked, then PLLs can be taken out of bypass mode. The Cortex™-A8 PLL is of this type. 

But after going through the section 2.6.7 "M2 & N2 Change On-the-Fly" I believe you can change the MPU frequency by changing the M2 divider alone on the fly. 

AM3874 TRM said:

The dividers M2 and N2 are designed to change on the fly. The output clock CLKOUT/ CLKOUTLDO perform a clean switch from OLD period to NEW period without any clock period being different from OLD or NEW period.

Also have you checked the section 7.4.6 in the datasheet am3874.pdf, where there is a  "PLL_ARM Simplified Block Diagram" given?

Dear Renjith-san,

Thank you for your detaied information.

I understand that the dividers M2 and N2 are dsigned to change on-the-fly. But, according to Figure7-17. PLL_ARM Simplified Block Diagram in datasheet,  it is used "N+1" input divider in PLL_ARM block. Is "N+1" divider designed to change on-the-fly? Also in same block, there is "N2+1" bypass divider. Is this devider valid only at reset?

Please adivse me. I appreciate your support.

Best regards,

Michi

Dear Michi-san,

I doubt whether M and N are supporting on the fly. But why do you need M and N to be configured. You can switch from 600 to 800 by reducing M2 alone I guess. 

Also how are you checking the BootROM has configured A8 to 600 MHz?

Generally BOOTROM configures A8 to bypass clock and the first level bootloader(u-boot) configures ti to appropriate clock. The first stage u-boot has the code to configure A8 to desired frequency, in DM8148. I have not worked on AM3874, but since it has similar architecture as DM8148, I believe same code will be used here also. 

There are macros defined in u-boot for M2 values. You can alter the value to get the desired frequency.