We have implemented the second workaround for Advisory 2.1.18 of the Silicion Errata for OMAP-L137 to solve the issue with the multiple interrupts reported by the AINTC for the CHIPINTn signals. We use the following code in our interrupt handler to clear the interrupt:
HWREG(CSL_SYSCFG_0_REGS + SYSCFG0_CHIPSIG_CLR) = 0x01;
HWREG(CSL_AINTC_0_REGS + AINTC_SICR) = 28;
However we sporadically get more than one interrupt using this workaround: in the error case the CHIPINTn signal is already cleared but the interrupt handler is invoked again. If we put some further instructions in between the two lines above the workaround seems to be stable. Is there any timing specification on the AINTC controller to know exactly when it is safe to clear the pending interrupt after the level interrupt has been de-asserted?
