Hello All,
I am in the process of trying to disable the EMIF-B DRAM interface while my processor is in deep sleep. The ARM side is what uses the DRAM and I have successfully halted the ARM and sent into an exception loop so it does not make any DRAM accesses.
Now my system is only running on the DSP side which makes no DRAM accesses. I am trying to disable the EMIF B module by following the procedure outlined in
SPRUH92A (OMAP-L137 Technical Technical Reference Manual). Thus far I am not able to confirm that the EMIF B module is powering down.
Here is the procedure as I understand it:
1. Place the EMIFB in self refresh mode before stoping the clock
I do this by setting the LP_MODE bit to 0 and the SR_PD bit to 1
Code:
// put memory into self-refresh mode
ddr_reg -> SDRCR &= ~SR_PD_BIT;
// select self-refresh mode (bit 23 to zero)
ddr_reg -> SDRCR |= LPMODEN_BIT;
// enable low-power mode (bit 31 to 1)
2. Next I turn off the clocks and power in the module by doing the following
ddr_reg -> SDRCR |= MCLKSTOP_EN;
DDRMCNTLREG = 2;
//Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
PTCMD = 2;
3. Then I wait for the GO[x] bit to clear to 0 to indicate DRAM module has transitioned to the new state.
At this point I should have effectively shut down the module, but when I look at the status bits for the EMIFB module, they still show the module as enabled.
There is a note in the manual that states the folllowing:
"The EMIFB memory controller remains fully functional during emulation halts, to allow emulation access to external memory."
Does this mean I can not shut the module down while in emulation?
Any help would be greatly appreciated. I'm sure the answer to this post will help many folks out.
Best Regards,
Lee Henderson
//Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
//after the GOSTAT[x] bit in PTSTAT is cleared to 0.
