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custom platform issues on evm6670



Hi ,
I am working on evm6670 and facing following issue. I have a sample piece of code which runs perfectly fine with the following config.bld.
(RTSC platform is set to ti.platforms.evm6670 and build configuration file is set to below mentioned config.bld.)

//config.bld
Build.platformTable["ti.platforms.evm6670"] =
{
    /* By default place code, data, stack sections on L2. Can be changed by application in .cfg/.cmd */
    codeMemory:         "L2SRAM",           
    dataMemory:         "L2SRAM",
    stackMemory:        "L2SRAM",

    l1DMode:            "0k",               /* Configure L1D as all SRAM. Can turn on Cache if needed at runtime */
    l1PMode:            "0k",               /* Configure L1P as all SRAM. Can turn on Cache if needed at runtime */
    l2Mode:                "0k",               /* Configure L2 as all SRAM. Can turn on Cache if needed at runtime */

    customMemoryMap:    
    [
        // GEM Local L2
        ["L2SRAM",
            {
                name:   "L2SRAM",
                base:   0x00800000,                    
                len:    0x00100000                    
            }
        ],
        // L1P. Comment this out if enabling L1P as all cache
        ["L1PSRAM",
            {
                name:   "L1PSRAM",
                base:   0x00E00000,                    
                len:      0x00008000
            }
        ],
        // L1D. Comment this out if enabling L1D as all cache
        ["L1DSRAM",
            {
                name:   "L1DSRAM",
                base:    0x00F00000,                    
                len:       0x00008000                   
            }
        ],
        ["MSMC_SHARED",
            {
                name:   "MSMC_SHARED_CORE012",
                base:    0x0c000000,                    
                len:        0x00003D80                   
            }
        ],
        ... other custom memory segments
    ]
};

Now if i create a new custom platform with the same memory segments, i observe some strange behaviors while running my software.
Same piece of code takes around 200K cycles with config.bld and it takes whopping 16000K cylces using custom platform.
Memory map generated by both config.bld and custom platform are exactly same except following.
  L2SRAM                00800000   00100000  000cc3ac  00033c54  RWIX  -- with config.bld
  L2SRAM                00800000   00100000  000cc3ac  00033c54  RWX   -- with custom platform.

We configure L2CACHE as 512 Kbytes using CACHE_setL2Size (CACHE_512KCACHE) api in main().

I have following questions ..

1.  Do you think this behavior is due to RWIX/RWX ? What is the significance of I in RWIX and how to set this attribute while defining a memory segment.
2.  Any pointers what could be going wrong or how to proceed forward ?


Thanks,
Ankit
   


  • Document SPRU186V (C6000 Assembly Tools Guide) defines the meaning of RWIX in Section 7.5.3.2 (MEMORY directive syntax):

    I - Specifies that the memory can be initialized.

    [Although I'm not sure if that makes things any clearer.]

  • Hi,

    it is not possible to  use L2SRAM as RAM and as cache at the same time (well, you can subdivide it into two partiotion, but I see that you configure the cache size to the maximum size). Try to move your code/data/stack memory onto MSMC. In your map file you L2SRAM allocated size should be zero.