AM3874 GPMC data bus(GPMC_AD[15-0]) timing specification

Michi Yama

Other Parts Discussed in Thread: AM3874

Hi,

I have one question regarding AM3874's GPMC Data bus(GPMC_AD[15-0]) timing speicification.

Our customer connets the external ASIC to GPMC of AM3874. As you know, GPMC_AD signals are bi-directional.

So customer would like to know the maximum timing that the ASIC may drive the data bus (GPMC_AD) line when the asynchronous read. Because ASIC's output signal may conflicts AM3874 address signal if this maximum value is not specified.

Please let me know the maximum time that the external device may drive to the data bus when GPMC asynchronous read. Or please let me know the guaranteed time that AM3874 drive the GPMC_AD data bus to HI-z state.

Best regards,

Michi

over 13 years ago

0 Biser Gatchev-XID over 13 years ago

TI__Guru**** 393215 points

Hi Michi,

The GPMC timing parameters are highly flexible and can be freely programmed. Please check section 8.8.2 of the datasheet and section 11.4.1 of the TRM for formulas and use cases.

Best Regards

Biser

0 Michi Yama over 13 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your reply.

As you said, GPMC timing parameters are flexible. And customer can set GPMC_CS and GPMC_OE timing freely. And address bus valid duration is decided by GPMC_CS valid to to GPMC_OE valid. Is my understandig right? If my understanding is right, the maximum value of the valid address duration is "No.30+No.14+No.38" in Figure 8-31 of datasheet. Is this right?

Please advise me.

Best regards,

Michi

0 Biser Gatchev-XID over 13 years ago in reply to Michi Yama

TI__Guru**** 393215 points

Hi Michi,

Yes, this is correct. Of course the maximum values should be taken from the table. By the way, there is a new datasheet available, from Sep. 14 2012:

http://www.ti.com/lit/ds/symlink/am3874.pdf

Best Regards

Biser

0 Michi Yama over 13 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your support.

I have one more question.

Please see the Figure 8-30 in datasheet. I attached its picture in the below.

Please check GPMC_AD[15:0] signal waveform. the first duration before Data OUT is shaded. What does this mean? Our customer worries that GPMC address signal is extended to this duration. But it means adddress and data bus is conflicted. Please let me know the meaning of shaded area, and address signal from GPMC does not exist in this duration.

Best regards,

Michi

0 Biser Gatchev-XID over 13 years ago in reply to Michi Yama

TI__Guru**** 393215 points

Hi Michi,

Shaded areas are "don't care". They are irrelevant to the current waveform.

Best Regards

Biser

0 Michi Yama over 13 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Biser-san,

Thank you for your quick reply.

When moving from Read access to Write access, this shaded area is no problem? When read access, the external device output data to GPMC_AD[15:0] line. Customer would like to know allowance timing that the externaldevice(ASIC) may output data to GPMC_AD[15:0]. Please let me know.

Best regards,

Michi

0 Biser Gatchev-XID over 13 years ago in reply to Michi Yama

TI__Guru**** 393215 points

Michi,

If you check Figure 8-27, the GPMC_AD[15:0] lines should be released by the ASIC after the moment GPMC_OE goes high (timing 5) and before the moment GPMC_CS[x] goes high (timing 2). The difference 2-5 will give you the time window that ASIC is allowed to hold the GPMC_AD[15:0] lines after GPMC_OE goes high.

Best Regards

Biser

0 Michi Yama over 13 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your support.

I would like to confirm one more thing.

In Figure 8-27, does AM3874 output something on the GPMC_AD[15:0] line after read cycle completed? In my understanding, AM3874 never output anything on GPMC_AD[15:0] after reacy cycle. Is it right?

Best regards,

Michi

0 Biser Gatchev-XID over 13 years ago in reply to Michi Yama

TI__Guru**** 393215 points

Hi Michi,

I think this is right. The GPMC_AD[15:0] will be switched to input at that time.

Best Regards

Biser

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AM3874 GPMC data bus(GPMC_AD[15-0]) timing specification