I2C1_SCL strange signal

Cyril BEGUET

On a board based on XAM3359ZCZ we observed a strange waveform on I2C1_SCL signal (pin A16 in mode 2). This is confirmed on BeagleBone.

On the beginning of rising edge, signal goes high very quickly (like a driven output), then signal oscillate and finally continue to rise free with the I2C pull-up resistor (like an open-drain output). (see pictures)

This is not observed on I2C1_SDA, I2C2_SCL nor I2C2_SDA !

When configuring I2C1_SCL pin in GPIO open-drain mode, no oscillation is observed and I2C_SCL rise like an open-drain output.

Has someone already observed that? Has someone an explanation?

over 12 years ago

0 Cyril BEGUET over 12 years ago

Intellectual 460 points

Measure on Beagle Bone :

Less oscillations but more "driven" output !

0 JJD over 12 years ago in reply to Cyril BEGUET

TI__Guru* 75990 points

Cyril, what code is running while you are capturing this scope shot? Is it possible that it is during a mode change?

Regards,

James

0 Cyril BEGUET over 12 years ago in reply to JJD

Intellectual 460 points

Hi James,

First waveform : runing U-boot command "i2c probe".

Second waveform (on Beagle Bone) : runing system test included into I2C IP on AM335x (I2C_SYSTEST Register)

Regards,

0 JJD over 12 years ago in reply to Cyril BEGUET

TI__Guru* 75990 points

Cyril, if it is occurring during i2c probe, it is most likely happening because of a padconfig mode change. Unless you are seeing this during normal clock cycles, this should not have any significance.

Regards,

James

0 Biser Gatchev-XID over 12 years ago in reply to JJD

TI__Guru**** 393215 points

Hi Cyril,

Is it possible that this strange signal is due to a missing/defective pullup on that I2C line. I've shown this to several people around the office here, and that's the general opinion. Please check the pullup resistor.

Best Regards

Biser

0 Cyril BEGUET over 12 years ago in reply to Biser Gatchev-XID

Intellectual 460 points

Hi,

Thank you for your answers.

I'will check that the observed edge is not the first of the I2C sequence.

Pull-ups look good because of a normal rising time after the strange part. And we don't see the problem on SDA line that have the same pull-up.

Best Regards

Cyril

0 Yaron dori over 12 years ago in reply to Cyril BEGUET

Prodigy 115 points

We have exact problem!

on I2C0

Bug in teh chip or BSP?

Yaron

0 Yaron dori over 12 years ago in reply to Yaron dori

Prodigy 115 points

We have done the same test on AM335EVM

result is the same.

SCL signal is not open drain, but rather pushed high at the first 10ns

Yaron

0 Yaron dori over 12 years ago in reply to Yaron dori

Prodigy 115 points

Hello

Further,

if you check RC calculation:

rise time in EVM: 10ns

pullups : 4.7k

=> bus capacitance = 1pf => impossible

Yaron

0 JJD over 12 years ago in reply to Yaron dori

TI__Guru* 75990 points

Is anyone seeing a functional issue with I2C? Or just this anomaly with the signal? I still think the cause is just a switching between mux modes, which does not happen during functional operation of the I2C interface.

Regards,

james

0 Cyril BEGUET over 12 years ago in reply to JJD

Intellectual 460 points

We also have functional issue with I2C. But I can't say if it's linked or not to the signal issue.

I will make a measure on monday to confirme if the switching comes juste on the first clock's front or on all of them.

Best Regards

Cyril

0 Yaron dori over 12 years ago in reply to JJD

Prodigy 115 points

James

this issue causes I2C bus freeze to endless "I2C timeouts"

that is why we started investigating in the first place

This happens both on uboot, and after kernel boots and file system is up, after the pins are properly configured. There should be no mux changes after configured in board-am33evm.c

Yaron

0 Cyril BEGUET over 12 years ago in reply to Cyril BEGUET

Intellectual 460 points

Hi,

Our I2C issue is not linked to the signal (but comes from a funny clock frequency reconfiguration from software).

The issue on the signal appears not only on the first edge of SCL but on every edge. If it's linked to a pad mode switching, it's on each edge. I don't know which part control this pin (HW chip or driver).

Cyril

0 Cyril BEGUET over 12 years ago in reply to Cyril BEGUET

Intellectual 460 points

Hi,

How goes investigations on this topic ?

We still don't have any answer to solve that !!

Cyril

0 peaves over 12 years ago in reply to Cyril BEGUET

TI__Guru 59175 points

Yes, we have looked at this issue and determined the cause.

The I2C outputs are implemented with push-pull 3-state output buffers. While it’s possible for the push-pull 3-state output buffer to behave as an open-drain output as required by I2C, there is a timing skew issue that causes the output to change before it is disabled. This causes the output buffer to drive a high logic level for a short time (0 - 5ns) each rising edge before the output is disabled.

Regards,
Paul

0 Cyril BEGUET over 12 years ago in reply to peaves

Intellectual 460 points

Thank you for this answer.

Is an correction planed ? An errata ?

Regards,

Cyril

0 peaves over 12 years ago in reply to Cyril BEGUET

TI__Guru 59175 points

We are in the process of creating an advisory for the silicon errata and evaluating a possible fix. However, we have not decided if and when this will be fixed.

Regards,
Paul

0 Randy Maruschock over 11 years ago in reply to peaves

Intellectual 320 points

For those of us starting new designs, is it possible to get a brief summary as to what impact this issue has? Are all or some of the I2C peripherals currently non-functional? Is there a planned fix in place yet? Has this been added to the errata (I don't see anything in the errata that mentions this)? I'd like to make sure I'm not creating a design that will be nonfunctional, or know what target dates exist for new silicon so that I know when I can make full use of the AM335x.

0 Biser Gatchev-XID over 11 years ago in reply to Randy Maruschock

TI__Guru**** 393215 points

Hi Randy,

As you have probably read above, this issue has been identified. It has impact only if I2C is used in multi-master mode or if there is slave clock stretching. This will be added in the revised Errata, due later this month. The new silicon revision should have this corrected, it should be available by the end of Q1, 2013.

0 Randy Maruschock over 11 years ago in reply to Biser Gatchev-XID

Intellectual 320 points

Thank you for the clarification. One more question though: are all three I2C ports affected? Or just specific ones?

0 Biser Gatchev-XID over 11 years ago in reply to Randy Maruschock

TI__Guru**** 393215 points

The issue is common for all I2C instances.

0 Randy Maruschock over 11 years ago in reply to Biser Gatchev-XID

Intellectual 320 points

Thank you!

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I2C1_SCL strange signal