The value returned by RMAN_assignResources function is IRES_ENORESOURCE...

zhao sun

Hi,

I tried to initialize 2 or more H264 baseline video codec's instance in the same thread base on the h264 video encoder unit test program running on c6678.

The first instance can be create successfully while the value returned by RMAN_assignResources function of the second instance is IRES_ENORESOURCE.

So how can I assign the same EDMA resource to 2 or more instance in the same thread? The calling sequence is as below:

RMAN_init();

ires_status = RMAN_assignResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId); //Codec instance 1 return IRES_OK

ires_status = RMAN_assignResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId); //Codec instance 2 return IRES_ENORESOURCE ... ...

The codecHandle above are different and the resFxns are the same. The RTSC config is set below:

RMAN.useDSKT2 = true;

RMAN.yieldSamePriority = true;

RMAN.tableSize = 10;

RMAN.maxAlgs = 10;

That is I want to create 10 instance of the same algorithm in the same thread. So how can I do that?

Thanks a lot!

B.R.

Sunzhao

over 13 years ago

0 Paula Carrillo over 13 years ago

TI__Mastermind 40580 points

Hi Zhao,

Which stand alone H.264 BP version are you using? also are you using persisten or scratch resources (scratchId)?

Thank you,

Paula

0 zhao sun over 13 years ago in reply to Paula Carrillo

Expert 1170 points

Hi Paula,

Thank you very much for your reply. The version of H.264 BP encoder used here

is C66x_h264venc_01_24_00_01_ELF. I have left the scratchId to -1 which is the

original value set in the unit testing program. I guess it maybe the reason that caused

I can not assign the same EDMA resource to 2 encoder instance because the attribute

of the resource is set to be persistent, right? But after I set the scratchId to 0 in the demo

program, and add the following content to the .cfg file to config scratch region 0. The first

RMAN_assignResources function return IRES_ENORESOURCE.

var META = xdc.useModule('ti.sdo.fc.edma3.Settings');

META.maxPaRams[0] = 42;

META.maxTccs[0] = 8;

META.maxEdmaChannels[0] = 8;

META.maxQdmaChannels[0] = 0;

META.eventQueueSetup = true;

...

So how can I assign the resource correctly to my codec instance? How can I assign the same

EDMA resource to 2 or more instance in the same thread(task)?

B.R.

Sunzhao

0 Paula Carrillo over 13 years ago in reply to zhao sun

TI__Mastermind 40580 points

Sunzhao,

how do you know IRES_ENORESOURCE is due to EDMA resources distribution issues? did you enable FC trace? if so could you please share the log?

http://processors.wiki.ti.com/index.php/Trace_in_Framework_Components#Run-Time_Code_for_Enabling_Logging

Thank you,

Paula

0 Hongmei Gou over 13 years ago in reply to zhao sun

TI__Expert 4335 points

Hi Sunzhao,

Starting from the H264BP encoder unit test, we tried and verified assigning RMAN resource to two encoder instances. Below are the suggested changes. The baseline and modified files are also attached below. Please diff them to find out the details.

1) Add the following lines in H264VEncApp6678.cfg

RMAN.maxAlgs = 10;

...

META.maxPaRams[0] = 42;
META.maxTccs[0] = 8;
META.maxEdmaChannels[0] = 8;
META.maxQdmaChannels[0] = 0;

2) Code change in alg_malloc.c to allow creating two codec instances. Basically, the internal memory is scratch memory and can be shared by multiple encoder instances. On the other hand, there is no overlapping between any two encoder instances for the buffers in external memory.

3) Code changes in TestAppEncoder.c including: a) use scratchId of 0 according to the addition in H264VEncApp6678.cfg; b) create the first encoder instance and do RMAN assign resource as before but do not check and set resActivatedFlag; d) create the second encoder instance, and do RMAN assign resource with algActivate and algDeactivate+Cache_wbInvAll around.

2084.E2E_RMAN.zip

Please try the above changes and let us know if you can assign RMAN resources to multiple encoder instances.

Thanks,

Hongmei

0 Anshul Maheshwari over 12 years ago in reply to Paula Carrillo

Intellectual 790 points

HI Paula

I was getting the same error and tried to enable FC trace but no prints are coming,

from framework.

i have attached my 4544.bios6.cfg file and 7433.logsetup.cfg

0 Hongmei Gou over 12 years ago in reply to Anshul Maheshwari

TI__Expert 4335 points

Hi Anshul,

Thanks for the files. It looks like you are trying to import "logsetup.cfg" to set up the FC trace log. However, settings imported from "logsetup.cfg" at the beginning of "bios6.cfg" can be overwritten due to the optimization settings in "bios6.cfg". This can be the reason why you are not seeing any prints. Also please remember to make the changes in C source files as indicated in http://processors.wiki.ti.com/index.php/Trace_in_Framework_Components.

In your attached bios6.cfg, ownerProcId in SharedRegion.setEntryMeta is changed from 0 to 1. Can you please let us know the motivation of making this change?

Thanks,

Hongmei

0 Anshul Maheshwari over 12 years ago in reply to Hongmei Gou

Intellectual 790 points

i removed the optimization things from makefile

i dont know if there are some optimization thing in bios6.cfg

I am not very good with this java scripts the language of bios6.cfg is as good as Chinese to me,

can you help me with where and (why there ) to put logsetup.cfg imorting line.

Why I changed OwnerProcId in SharedRegion.setEntryMeta from 0 to 1 ::-

actually to run sv04 it was neccasary to load the code on first core.

i was having another code which was also having dependency of loading it on core 0

so i was trying to remove the dependency, i suggest shared region should be some what more dynamic, then what is it now , taking ownerProcId from core team mapping

Added code to c file as indicated in link

except this line

/* Now call DSKT2_createAlg */
alg = DSKT2_createAlg(scratchId, fxns, NULL, (IALG_Params *)&params);

every thing was already there. and i even feel like is that line really important.

attached

Fullscreen 3036.siuFcBios6.c Download

/******************************************************************************
 * FILE PURPOSE: Using FC which is based on BIOS 6
 ******************************************************************************
 * FILE NAME:   siuFcBios6.c
 *
 * DESCRIPTION: Contains FC related functions
 *
 * TABS: NONE
 *
 *
 * (C) Copyright 2011, Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#include <xdc/std.h>
#include <xdc/runtime/Diags.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Memory.h>

#include <ti/xdais/ires.h>

#include <ti/sysbios/heaps/HeapMem.h>

#include <ti/sdo/fc/edma3/edma3_config.h>
#include <ti/sdo/fc/rman/rman.h>
#include <ti/sdo/fc/dskt2/dskt2.h>
#include <ti/sdo/fc/ecpy/ecpy.h>
#include <ti/sdo/fc/ires/edma3chan/iresman_edma3Chan.h>

/* Get globals from cfg header */
#include <xdc/cfg/global.h>

#include "osal/siuFcOsal.h"
#include "common/siuloc.h"

#define FC_TRACE
#ifdef FC_TRACE
#include <ti/sdo/fc/global/FCSettings.h>
#endif

/* Definition of EDMA3_InstanceInitConfig structure from                    */
/* <ti/sdo/fc/edma3/edma3_config.h>. It is attached here and put under      */
/* #if 0 for reference                                                      */

/* EDMA3_InstanceInitConfig is init-time Region Specific Configuration      */
/* structure for EDMA3 to provide region specific Information. It is used   */
/* to specify which EDMA3 resources are owned and reserved by the EDMA3     */
/* instance.                                                                */

#if 0
typedef struct
{
    unsigned int        ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
                            /**< PaRAM Sets owned by the EDMA3 RM Instance. */
    unsigned int        ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
                            /**< DMA Channels owned by the EDMA3 RM Instance. */
    unsigned int        ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
                            /**< QDMA Channels owned by the EDMA3 RM Instance.*/
    unsigned int        ownTccs[EDMA3_MAX_TCC_DWRDS];
                            /**< TCCs owned by the EDMA3 RM Instance. */
    /**
     * @brief       Reserved PaRAM Sets
     */
    unsigned int        resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
    /**
     * @brief       Reserved DMA channels
     */
    unsigned int        resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
    /**
     * @brief       Reserved QDMA channels
     */
    unsigned int        resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
    /**
     * @brief       Reserved TCCs
     */
    unsigned int        resvdTccs[EDMA3_MAX_TCC_DWRDS];
} EDMA3_InstanceInitConfig;
#endif

/* In the arrays below, each bit of a 32-bit word corresponds to a single   */
/* PaRAMSet/EDMAChannel/QDMAChannel/TCC owned by the corresponding region,  */
/* i.e., can be used for general purpose EDMA tranfers, or reserved for     */
/* EDMA transfers by hardware peripherals (cannot be used for general       */
/* purpose EDMA tranfers)                                                   */

#define DMA_CHANNEL_TO_EVENT_MAPPING_0          (0x00C00000u)
#define DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x00000000u)

/* EDMA3_InstanceInitConfig sample0 with region neither owning nor          */
/* reserving any EDMA resources                                             */
#define regionSample0                                         \
{                                                             \
    /* Resources owned by Region */                           \
    /* ownPaRAMSets */                                        \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* ownDmaChannels */                                      \
    {0x00000000u, 0x00000000u},                               \
                                                              \
    /* ownQdmaChannels */                                     \
    {0x00000000u},                                            \
                                                              \
    /* ownTccs */                                             \
    {0x00000000u, 0x00000000u},                               \
                                                              \
    /* Resources reserved by Region */                        \
    /* resvdPaRAMSets */                                      \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* resvdDmaChannels */                                    \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
                                                              \
    /* resvdQdmaChannels */                                   \
    {0x00000000u},                                            \
                                                              \
    /* resvdTccs */                                           \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
}

/* EDMA3_InstanceInitConfig sample1 with region owning PaRAM sets 64-105,   */
/* and EDMA channel 0-7, but not reserving any EDMA resources               */
/* Note that the first N PaRAM sets (N=number of EDMA channels available    */
/* on an EDMA instance) are reserved in EDMA3 LLD ).                        */
#define regionSample1                                         \
{                                                             \
    /* Resources owned by Region */                           \
    /* ownPaRAMSets */                                        \
    {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,      \
     0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* ownDmaChannels */                                      \
    {0x0000FFFFu, 0x00000000u},                               \
                                                              \
    /* ownQdmaChannels */                                     \
    {0x00000000u},                                            \
                                                              \
    /* ownTccs */                                             \
    {0x0000FFFFu, 0x00000000u},                               \
                                                              \
    /* Resources reserved by Region */                        \
    /* resvdPaRAMSets */                                      \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* resvdDmaChannels */                                    \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
                                                              \
    /* resvdQdmaChannels */                                   \
    {0x00000000u},                                            \
                                                              \
    /* resvdTccs */                                           \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
}


/* EDMA3_InstanceInitConfig sample2 with region owning PaRAM sets 106-147,  */
/* and EDMA channel 8-15, but not reserving any EDMA resources               */
#define regionSample2                                         \
{                                                             \
    /* Resources owned by Region */                           \
    /* ownPaRAMSets */                                        \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* ownDmaChannels */                                      \
    {0xFF3F0000u, 0x00000000u},                               \
                                                              \
    /* ownQdmaChannels */                                     \
    {0x00000000u},                                            \
                                                              \
    /* ownTccs */                                             \
    {0xFF3F0000u, 0x00000000u},                               \
                                                              \
    /* Resources reserved by Region */                        \
    /* resvdPaRAMSets */                                      \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* resvdDmaChannels */                                    \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
                                                              \
    /* resvdQdmaChannels */                                   \
    {0x00000000u},                                            \
                                                              \
    /* resvdTccs */                                           \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
}

/* EDMA3_InstanceInitConfig sample3 with region owning PaRAM sets 148-189,  */
/* and EDMA channel 16-23, but not reserving any EDMA resources             */
#define regionSample3                                         \
{                                                             \
    /* Resources owned by Region */                           \
    /* ownPaRAMSets */                                        \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,      \
     0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* ownDmaChannels */                                      \
    {0x00000000u, 0x0000FFFFu},                               \
                                                              \
    /* ownQdmaChannels */                                     \
    {0x00000000u},                                            \
                                                              \
    /* ownTccs */                                             \
    {0x00000000u, 0x0000FFFFu},                               \
                                                              \
    /* Resources reserved by Region */                        \
    /* resvdPaRAMSets */                                      \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* resvdDmaChannels */                                    \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
                                                              \
    /* resvdQdmaChannels */                                   \
    {0x00000000u},                                            \
                                                              \
    /* resvdTccs */                                           \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
}

/* EDMA3_InstanceInitConfig sample4 with region owning PaRAM sets 190-231,  */
/* and EDMA channel 24-31, but not reserving any EDMA resources             */
#define regionSample4                                         \
{                                                             \
    /* Resources owned by Region */                           \
    /* ownPaRAMSets */                                        \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* ownDmaChannels */                                      \
    {0x00000000u, 0xFFFF0000u},                               \
                                                              \
    /* ownQdmaChannels */                                     \
    {0x00000000u},                                            \
                                                              \
    /* ownTccs */                                             \
    {0x00000000u, 0xFFFF0000u},                               \
                                                              \
    /* Resources reserved by Region */                        \
    /* resvdPaRAMSets */                                      \
    {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,      \
     0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},     \
                                                              \
    /* resvdDmaChannels */                                    \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
                                                              \
    /* resvdQdmaChannels */                                   \
    {0x00000000u},                                            \
                                                              \
    /* resvdTccs */                                           \
    {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
}

const EDMA3_InstanceInitConfig C6608_config[3][8] =
{
 /* EDMA3 INSTANCE# 0 */
 { regionSample0,  regionSample0,  regionSample0,  regionSample0,
   regionSample0,  regionSample0,  regionSample0,  regionSample0
 },
 /* EDMA3 INSTANCE# 1 */
 { regionSample1,  regionSample2,  regionSample3,  regionSample4,
   regionSample0,  regionSample0,  regionSample0,  regionSample0
 },
 /* EDMA3 INSTANCE# 2 */
 { regionSample0,  regionSample0,  regionSample0,  regionSample0,
   regionSample1,  regionSample2,  regionSample3,  regionSample4
 }
};

#ifdef FC_RUN_TIME_HEAP
typedef struct biosFcContext_s {
    ti_sysbios_heaps_HeapMem_Handle INTMEM_HEAP;      /* Heap in Local L2 */
    #define NUM_SCRATCH 2                           /* Two scratch groups: one for codec, one for framework */
    ti_sysbios_heaps_HeapMem_Handle INTSCRATCH_HEAP[NUM_SCRATCH];  /* Scratch in Local L2 */
    ti_sysbios_heaps_HeapMem_Handle EXTMEM_HEAP;      /* Heap in Local DDR */
    #define NUM_ALG (SIU_MAX_TDM_CHANNELS)          /* Number of alg instances*/
    IALG_Handle alg_handle[NUM_SCRATCH][NUM_ALG];   /* Array to store ALG handles */
} biosFcContext_t;

biosFcContext_t fc_context;

/*********************************************************************************
 * FUNCTION PURPOSE: Create FC heaps
 *********************************************************************************
  DESCRIPTION:      This function is creating heaps for FC use. There are heaps
                    from local L2, MSMC, and DDR.
                    Note that after MPAX is working with MSMC, MSMC shall be
                    handled in the same way as DDR.

  Parameters :      Inputs: msmcHeapBegin : base of MSMC heap
                            msmcHeapSize  : size of MSMC heap
                    Output: None
 *********************************************************************************/
void siu_fc_heap_create(void)
{
    HeapMem_Params prms;
    extern unsigned char _lcf_bios_fc_external_heap_begin;
    extern unsigned char _lcf_bios_fc_external_heap_end;
    extern unsigned char _lcf_bios_fc_internal_heap_begin;
    extern unsigned char _lcf_bios_fc_internal_heap_end;
    extern unsigned char _lcf_bios_fc_internal_scratch1_begin;
    extern unsigned char _lcf_bios_fc_internal_scratch1_end;
    extern unsigned char _lcf_bios_fc_internal_scratch2_begin;
    extern unsigned char _lcf_bios_fc_internal_scratch2_end;
    Int i, j;

    /* Create internal heap */
    HeapMem_Params_init(&prms);
    prms.size = &_lcf_bios_fc_internal_heap_end - &_lcf_bios_fc_internal_heap_begin;
    prms.buf = (Ptr)&_lcf_bios_fc_internal_heap_begin;
    fc_context.INTMEM_HEAP = HeapMem_create(&prms, NULL);

    /* Create internal scratches */
    HeapMem_Params_init(&prms);
    prms.size = &_lcf_bios_fc_internal_scratch1_end - &_lcf_bios_fc_internal_scratch1_begin;
    prms.buf = (Ptr)&_lcf_bios_fc_internal_scratch1_begin;
    fc_context.INTSCRATCH_HEAP[0] = HeapMem_create(&prms, NULL);
    
    prms.size = &_lcf_bios_fc_internal_scratch2_end - &_lcf_bios_fc_internal_scratch2_begin;
    prms.buf = (Ptr)&_lcf_bios_fc_internal_scratch2_begin;
    fc_context.INTSCRATCH_HEAP[1] = HeapMem_create(&prms, NULL);

    /* Create external heap */
    HeapMem_Params_init(&prms);
    prms.size = &_lcf_bios_fc_external_heap_end - &_lcf_bios_fc_external_heap_begin;
    prms.buf = (Ptr)&_lcf_bios_fc_external_heap_begin;
    fc_context.EXTMEM_HEAP = HeapMem_create(&prms, NULL);

    /* Initialization */
    for (i = 0; i < NUM_SCRATCH; i++) {
        for (j = 0; j < NUM_ALG; j++) {
            fc_context.alg_handle[i][j] = NULL;
        }
    }
}

/*********************************************************************************
 * FUNCTION PURPOSE: Free local L2 heap memory
 *********************************************************************************
  DESCRIPTION:      This function frees Local L2 heap memory

  Parameters :      Inputs: memTab  : memory entries
                            n       : number of memory entries
                    Output: None
 *********************************************************************************/
Void siuFcFreeIntMemory(IALG_MemRec memTab[], Int n)
{
    Int i;
    for (i = 0; i < n; i++) {
        if (memTab[i].base != NULL) {
            Memory_free((xdc_runtime_IHeap_Handle)fc_context.INTMEM_HEAP,
                         memTab->base, memTab->size);
        }
    }
}

/*********************************************************************************
 * FUNCTION PURPOSE: Allocate local L2 heap memory
 *********************************************************************************
  DESCRIPTION:      This function allocates Local L2 heap memory

  Parameters :      Inputs: memTab  : memory entries
                            n       : number of memory entries
                    Output: TRUE if allocation successful; FALSE otherwise
 *********************************************************************************/
Bool siuFcAllocIntMemory(IALG_MemRec memTab[], Int n)
{
    Int i;
    for (i = 0; i < n; i++) {
        memTab[i].base = Memory_calloc((xdc_runtime_IHeap_Handle)fc_context.INTMEM_HEAP,
                                       memTab[i].size, memTab[i].alignment, NULL);
        if (memTab[i].base == NULL) {
            siuFcFreeIntMemory(memTab, i);
            return (FALSE);
        }
    }
    return (TRUE);
}

/*********************************************************************************
 * FUNCTION PURPOSE: Free DDR heap memory
 *********************************************************************************
  DESCRIPTION:      This function frees DDR heap memory

  Parameters :      Inputs: memTab  : memory entries
                            n       : number of memory entries
                    Output: None
 *********************************************************************************/
Void siuFcFreeExtMemory(IALG_MemRec memTab[], Int n)
{
    Int i;
    for (i = 0; i < n; i++) {
        if (memTab[i].base != NULL) {
            Memory_free((xdc_runtime_IHeap_Handle)fc_context.EXTMEM_HEAP,
                        memTab->base, memTab->size);
        }
    }
}

/*********************************************************************************
 * FUNCTION PURPOSE: Allocate DDR heap memory
 *********************************************************************************
  DESCRIPTION:      This function allocates DDR heap memory

  Parameters :      Inputs: memTab  : memory entries
                            n       : number of memory entries
                    Output: TRUE if allocation successful; FALSE otherwise
 *********************************************************************************/
Bool siuFcAllocExtMemory(IALG_MemRec memTab[], Int n)
{
    Int i;
    for (i = 0; i < n; i++) {
        memTab[i].base = Memory_calloc((xdc_runtime_IHeap_Handle)fc_context.EXTMEM_HEAP,
                                       memTab[i].size, memTab[i].alignment, NULL);
        if (memTab[i].base == NULL) {
            siuFcFreeExtMemory(memTab, i);
            return (FALSE);
        }
    }
    return (TRUE);
}

/*********************************************************************************
 * FUNCTION PURPOSE: Free scratch memory
 *********************************************************************************
  DESCRIPTION:      This function frees scratch memory

  Parameters :      Inputs: mutexId  : Scratch ID
                            addr     : Address of memory to be freed
                            size     : Size of memory to be freed
                    Output: None
 *********************************************************************************/
Void siuFcFreeScratchMemory(Int mutexId, Void *addr, UInt size)
{
    /* Simply return without doing any memory free actions. Scratch handle
       will be restored next time when scratch alloc is called.           */
    return;
}


/*********************************************************************************
 * FUNCTION PURPOSE: Allocate scratch memory
 *********************************************************************************
  DESCRIPTION:      This function allocates scratch memory

  Parameters :      Inputs: alg        : IALG handle
                            mutexId    : Scratch ID
                            memTab     : memory entries
                            numRecs    : number of memory entries
                    Output: TRUE if allocation successful; FALSE otherwise
 *********************************************************************************/
Bool siuFcAllocScratchMemory(IALG_Handle alg, Int mutexId, IALG_MemRec *memTab, Int numRecs)
{
    Int i, j;    

    for (i = 0; i < NUM_ALG; i++) {
        if(alg == fc_context.alg_handle[mutexId][i]) {
            break;
        }
    }
    if( i == NUM_ALG) {
        /* Handle is not found from the iag handle array */
        /* Restore the scratch handle  */
        HeapMem_restore((HeapMem_Handle)fc_context.INTSCRATCH_HEAP[mutexId]);
        /* Record the alg handle */
        for (j = 0; j < NUM_ALG; j++) {
            if(fc_context.alg_handle[mutexId][j] == NULL) {
                fc_context.alg_handle[mutexId][j] = alg;
                break;
            }
        }
        siu_exc_assert (j < NUM_ALG, SIUVIGDK_EXC_FC_ALG_ARRAY_OVERFLOW, &siuContext);
    }

    for (i = 0; i < numRecs; i++) {
        if (memTab[i].attrs == IALG_SCRATCH) {
            memTab[i].base = Memory_calloc((xdc_runtime_IHeap_Handle)fc_context.INTSCRATCH_HEAP[mutexId],
                                            memTab[i].size, memTab[i].alignment, NULL);
        }
    }

    return (TRUE);
}

/*********************************************************************************
 * FUNCTION PURPOSE: Get scratch ID
 *********************************************************************************
  DESCRIPTION:      This function returns scratch ID

  Parameters :      Inputs: IALG_Handle  : IALG handle
                    Output: Scratch ID
 *********************************************************************************/
Int siuFcGetScratchId(IALG_Handle alg)
{   
  if( alg == (IALG_Handle)&siuContext.edmaFwState) {
    return (1);
  } else {
    return(0);
  }
}
#endif

/*********************************************************************************
 * FUNCTION PURPOSE: Init RMAN resources
 *********************************************************************************
  DESCRIPTION:      This function initializes RMAN resouces

  Parameters :      Inputs: edmaInstanceId  : ID of EDMA instance to be used
                            edmaQueueId     : Queue ID
                            coreId          : core ID
                            runtimeHeap     : flag indicating if heaps are
                                              created at run time
                    Output: TRUE if initialization successful; FALSE otherwise
 *********************************************************************************/
bool siu_osal_fc_resoure_init(unsigned int edmaInstanceId, unsigned int edmaQueueId,
                              unsigned int coreId, bool runtimeHeap)
{
    EDMA3_PARAMS.regionConfig = (EDMA3_InstanceInitConfig *)&C6608_config[edmaInstanceId][coreId];
    IRES_Status             ires_status;

    /* create internal/external heaps */
#ifdef FC_RUN_TIME_HEAP
    if(runtimeHeap) {
      siu_fc_heap_create();
    }
#endif

#ifdef FC_TRACE
    /* Set default mask for FC modules */
    FCSettings_init();
    Diags_setMask(FCSETTINGS_MODNAME"+EX1234567");
#endif

    /* specify EDMA instance ID and queue ID */
    ti_sdo_fc_edma3_EDMA3_physicalId = edmaInstanceId;
    ti_sdo_fc_edma3_Settings_defaultQ = edmaQueueId;

    /* RMAN init */
    ires_status = RMAN_init();

    if (IRES_OK != ires_status) {
        return FALSE;
    }
    return TRUE;
}

/*********************************************************************************
 * FUNCTION PURPOSE: Assign and activate RMAN resources
 *********************************************************************************
  DESCRIPTION:      This function assigns and activates RMAN resouces

  Parameters :      Inputs: codecHandle   : codec handle
                            resFxns       : IRES function pointers
                    Output: TRUE if initialization successful; FALSE otherwise
 *********************************************************************************/
bool siu_osal_fc_assign_resources(void* codecHandle, void* resFxns, siuFcUser_t user)
{
    IRES_Status ires_status;
    Int scratchId = -1; 
    
    if(user ==SIU_FC_USER_CODEC) {
        scratchId = 0;
    } else if (user == SIU_FC_USER_FRAMEWORK) {
        scratchId = 1;
    }

    /* RMAN assign resource */
    ires_status = RMAN_assignResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId);
    if (ires_status != IRES_OK) {
        return FALSE;
    }

    /* RMAN activate all resource */
    RMAN_activateAllResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId);
    return TRUE;
}

/*********************************************************************************
 * FUNCTION PURPOSE: Free RMAN resources
 *********************************************************************************
  DESCRIPTION:      This function frees RMAN resouces

  Parameters :      Inputs: codecHandle   : codec handle
                            resFxns       : IRES function pointers
                    Output: TRUE if free is successful; FALSE otherwise
 *********************************************************************************/
bool siu_osal_fc_free_resources(void* codecHandle, void* resFxns, siuFcUser_t user)
{
    IRES_Status ires_status;
    Int scratchId = -1; 
    Int i;

    if(user ==SIU_FC_USER_CODEC) {
        scratchId = 0;
    } else if (user == SIU_FC_USER_FRAMEWORK) {
        scratchId = 1;
    }

    /* RMAN free resource */
    ires_status = RMAN_freeResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId);
    if (ires_status != IRES_OK) {
        return FALSE;
    }

#ifdef FC_RUN_TIME_HEAP
    /* Remove alg handle from the array of fc_context.alg_handle
       With this removed, scratch handle will be restored next time
       when scratch alloc is called for the alg. */
    for (i = 0; i < NUM_ALG; i++) {
        if(codecHandle == fc_context.alg_handle[scratchId][i]) {
            fc_context.alg_handle[scratchId][i] = NULL;
            break;
        }
    }
#endif
    return TRUE;
}

thanks

anshul

0 Hongmei Gou over 12 years ago in reply to Anshul Maheshwari

TI__Expert 4335 points

Hi Anshul,

Do you have JTAG for the debugging now? FC traces needs to show up in CCS Console. If you have JTAG to connect to CCS, you can also step into FC code to find out why the error code is returned. Before doing that, please use debug mode for FC and EDMA3LLD in bios6.cfg:

/* Uncomment this to use debug mode for FC and EDMA3 */
xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug";
EDMA3LLD.profile = "debug";

Also in CCS, you can check if there is any error (such as stack overflow, memory overflow, exception, and etc.) in ROV (RTSC Object View).

Thanks,

Hongmei

0 Anshul Maheshwari over 12 years ago in reply to Hongmei Gou

Intellectual 790 points

its not exactly the jtag but it is simulator of c6678 given with ccs.

If you look at bios.cfg attached in above reply those are already un commented.

i tried even "you can also step into FC code to find out why the error code is returned"

but code of fc code is not compiled on my pc, so too difficult to load the symbol and locate the file,

many time source code does not match with located file, so its too difficult to debug without compiling

source code, i have to look at code using diassembly view.

and i really got to error by edma. but the reson why that error goes above my head,

does rov mean rtos object view :: dont know how to use it. i can look at heap mem (used and unused )but stack no idea

Actually i am getting "IRES_ENORESOURCE" already specified by zaho

in rman.c "file from framework component "

                resDesc[n].handle = resman->getHandle(alg, &resDesc[n],
                        scratchGroupId, &status);

                /* Release lock */
                IGateProvider_leave(gate, key);

                if (IRES_OK != status) {
                    break;
                }

function called are as below

> RMAN_assignResources

>> siu_osal_fc_assign_resources

>>> xdm2p0_vid_enc_create

>>>> siuVctRunMediaConfigReq

>>>> siuVctRunTask

looked more deeper and found that below condition was true

    /* Check if the resources have been requested properly,
     * fail if there is an error */
    if ((numPaRams > 0) && (!(_resmanInternalState->dchmapExists))) {

        if ((numPaRams > 1) &&
                (IRES_EDMA3CHAN_CHAN_NONE != reqEdma)) {

            *status = IRES_ENORESOURCE;

            Log_print0(Diags_USER7,
                    "[+7] IRESMAN_EDMA3CHAN_getHandles> Cannot request multiple "
                    " paRams alongwith an EDMA3 channel when DCHMAP does not"
                    "exist. Request only one PaRam alongwith EDMA channel or "
                    "only multiple PaRams with no EDMA channel per handle");

            if (EDMA3_SOK != EDMA3_releaseResourceManager(algHandle,
                    scratchGroupId)) {

                *status = IRES_EFAIL;

                Log_print0(Diags_USER7,
                        "[+7] IRESMAN_EDMA3CHAN_getHandles> Error releasing Low "
                        "level Resource Manager Handle.");
            }

            Log_print0(Diags_EXIT,
                    "[+X] IRESMAN_EDMA3CHAN_getHandles> Exit (handle=NULL, "
                    "status=IRES_ENORESOURCE)");

            return (NULL);
        }

" Dont you think we are again diverting from my question, i wanted to enable fc trace"

thanks

anshul

0 Gunjan over 12 years ago in reply to Anshul Maheshwari

TI__Expert 7415 points

Anshul,

The "C" based lines you have added in your "C" files look right to me. I'd like to inspect your latest config file if you can share them with me please.

The call stack you have indicated as the error point, point to a badly formed request from the codec. If you haven't modified the codec in any way, it seems unlikely that this is the point of failure.

Hopefully we can fix your cfg file so you should start seeing some trace soon.

Thanks,

Gunjan

0 Anshul Maheshwari over 12 years ago in reply to Gunjan

Intellectual 790 points

hi gunjan

i have already posted the cfg files in my previous reply

no change in them since upload of those file

sorry to say that but those "c" based line are not added by me, but that are shipped with mcsdk video demo sv04

no change from my side.

I tried to build the example in framework component, and osal package was needed to be downloaded.

from http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/osal/1_23_00_04/index_FDS.html

but at last it was still not built giving me linker error

-D_DEBUG_=1 --symdebug:dwarf   -eo.o66elf -fr=bin/debug app.c
#
# Making bin/debug/dskt2_example_coreN.x66elf ...
/home/anshul/ti/TI_CGT_C6000_7.4.0/bin/lnk6x -o bin/debug/dskt2_example_coreN.x66elf -q --compress_dwarf -w -q -u _c_int00 -c -I/home/anshul/ti/xdctools_3_24_05_48/packages -I/home/anshul/ti/framework_components_3_23_02_16/packages -I/home/anshul/ti/bios_6_34_02_18/packages -I/home/anshul/ti/xdais_7_23_00_06/packages -I/home/anshul/ti/osal_1_23_00_04/packages -I/home/anshul/ti/edma3_lld_02_11_05_02/packages -I/home/anshul/ti/framework_components_3_23_02_16/examples bin/debug/main_BIOS.o66elf bin/debug/app.o66elf local/linker.cmd local_debug_66elf.cmd -l /home/anshul/ti/TI_CGT_C6000_7.4.0/lib/rts6600_elf.lib -l"../codec/lib/debug/dskt2_example.a66elf" -m bin/debug/dskt2_example_coreN.x66elf.map
error: file "../codec/lib/debug/dskt2_example.a66elf<iusescratch.o66elf>"
   aligns arrays to 4 bytes, but previous files expect arrays to be aligned to
   8 bytes
error: file
   "../codec/lib/debug/dskt2_example.a66elf<usescratch_ti_vtab.o66elf>" aligns
   arrays to 4 bytes, but previous files expect arrays to be aligned to 8
   bytes
error: file "../codec/lib/debug/dskt2_example.a66elf<usescratch_ti.o66elf>"
   aligns arrays to 4 bytes, but previous files expect arrays to be aligned to
   8 bytes
error: errors encountered during linking;
   "bin/debug/dskt2_example_coreN.x66elf" not built
gmake[3]: *** [bin/debug/dskt2_example_coreN.x66elf] Error 1
gmake[3]: Leaving directory `/home/anshul/ti/framework_components_3_23_02_16/examples/ex02_dskt2_alg_mgmt/app'

thanks

anshul

http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/osal/1_23_00_04/index_FDS.html

0 Gunjan over 12 years ago in reply to Anshul Maheshwari

TI__Expert 7415 points

Anshul,

If you haven't changed your files from before, then as Hongmei mentioned settings imported from "logsetup.cfg" are being overwritten at the beginning of "bios6.cfg". So you will not see the effect of those changes.

In particular, you set up the logger in logsetup.cfg like this:-

Defaults.common$.logger = LoggerSys.create(LoggerSysParams);

And then you overwrite it in bios.cfg like this:-

Defaults.common$.logger = null;

Make sure you remove everything in bios.cfg that has to do with Logging and Diags, in particular these lines

/* Optimization */
Diags = xdc.useModule("xdc.runtime.Diags");
var Defaults = xdc.useModule('xdc.runtime.Defaults');
Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF
Defaults.common$.logger = null;

In logsetup.cfg, at the end you can add these lines:-

Defaults.common$.diags_ENTRY = Diags.RUNTIME_OFF;
Defaults.common$.diags_EXIT = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER1 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER2 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER3 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER4 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER5 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER6 = Diags.RUNTIME_OFF;
Defaults.common$.diags_USER7 = Diags.RUNTIME_OFF;

Assuming you have kept your "C" code the way it was (with the Diags_setMask statement), you should now have everything to enable logging. Try doing a clean build of your app and run it on the simulator.

You should be seeing some trace on the CCS Console.

0 Paula Carrillo over 12 years ago in reply to Gunjan

TI__Mastermind 40580 points

Hi Anshul, wondering if now you are able to see FC trace?

Thank you,

Paula

0 Anshul Maheshwari over 12 years ago in reply to Paula Carrillo

Intellectual 790 points

hi paula

still i cant see any trace.

hi gunjan

i did those change, but they dont have any effect.

my cfg files are below

4130.bios6.cfg

3704.logsetup.cfg

thanks

anshul

0 Paula Carrillo over 12 years ago in reply to Anshul Maheshwari

TI__Mastermind 40580 points

Anshul, as an exercise I enabled FC trace on MCSDK video example transcoder. I used first my board and then the Shannon simulator. On both I am getting correctly FC trace printed on CCS console.. of course, because the Transcoder uses TFTP when I am using the simulator it hangs reading TFTP file (trying to find DSP ip address) but anyhow this was just a quick test. Please see attached bios.cfg and videoTranscode.cfg. I mainly used changes previously suggested by Hongmei and Gunjan.

7115.videoTranscode.cfg

6320.bios6.cfg

One thing that I noticed on your logsetup.cfg was that you define twice "var Defaults"

var Defaults = xdc.useModule('xdc.runtime.Defaults');

Defaults.common$.logger = LoggerSys.create(LoggerSysParams);

var Defaults = xdc.useModule('xdc.runtime.Defaults');

No sure if this could be an issue but you can try deleting the last one.

>>>>>>>CCS console / using simulator>>>>>>>>>>>>>>>>

TMS320C66x_0] [t=0x00086eba] ti.sdo.fc.rman: [+E] RMAN_init> Enter

[TMS320C66x_0] [t=0x0008aacb] ti.sdo.fc.rman: [+E] RMAN_register> Enter (resmanFxns=0x856f2c, initArgs=0x8598bc)

[TMS320C66x_0] [t=0x000902af] ti.sdo.fc.rman: [+4] RMAN_register> Registering protocol ti.sdo.fc.ires.examples.resources.nullres revision (1.0.0)

[TMS320C66x_0] [t=0x0009ad7a] ti.sdo.fc.rman: [+X] RMAN_register> Exit (status=IRES_OK)

[TMS320C66x_0] [t=0x0009edc2] ti.sdo.fc.rman: [+2] RMAN_init> Registering statically added resources

[TMS320C66x_0] [t=0x000a382a] ti.sdo.fc.rman: [+E] RMAN_register> Enter (resmanFxns=0x856fec, initArgs=0x852b20)

[TMS320C66x_0] [t=0x000a9069] ti.sdo.fc.rman: [+4] RMAN_register> Registering protocol ti.sdo.fc.ires.edma3chan revision (2.0.0)

[TMS320C66x_0] [t=0x000b2e88] ti.sdo.fc.ires.edma3chan: [+E] IRESMAN_EDMA3CHAN_init> Enter (initArgs=0x852b20)

[TMS320C66x_0] [t=0x000bb9ad] ti.sdo.fc.ires.edma3chan: [+X] IRESMAN_EDMA3CHAN_init> Exit (status=0)

[TMS320C66x_0] [t=0x000c0561] ti.sdo.fc.rman: [+X] RMAN_register> Exit (status=IRES_OK)

[TMS320C66x_0] [t=0x000c47ca] ti.sdo.fc.rman: [+X] RMAN_init> Exit (status=0)

[TMS320C66x_0] Read tftp config file

Thank you,

Paula

0 Anshul Maheshwari over 12 years ago in reply to Paula Carrillo

Intellectual 790 points

hi paula

even i was not facing any problem, with that video_transcode example, so never thought to enable traces in it.

i was using sv04 binary when i got those error and thought to enable traces, if you have mcsdk_video set up ready please give it a try.

when all my way were dark to me, I was trying to build example given in framework component and enabling traces but i failed to do so!!!

should i start new post for failure example in framework component, even if u answer my question, this one not marked as answer.

thanks

anshul

0 Paula Carrillo over 12 years ago in reply to Anshul Maheshwari

TI__Mastermind 40580 points

Anshul, apologize, I was under the impression you were working on a transcoder using as a base our transcoder example, but anyhow, please see attached bios6.cfg, you can find added and commeted lines searching for PC--. Mainly what I did was merge your logsetup.cfg on bios6.cfg being careful nothing get overwritted by the original bios6.cfg. I tested H264 HP TFTP encoder (SV04) on the board and on the Shannon simulator. Both showed correctly FC trace.

Please after modify bios6.cfg rebuild SV04. If you are in windows environment in a console run the batch file "\dsp\mkrel\setupenvMsys.bat bypass" in order to execute src\dsp\mkrel\setupenvMsys.sh and enters shell. Then "make" the video application

bash-3.1$ make sv04 "FLAT=YES"

Output program would be at: /mkrel/sv04/flat

7558.bios6.cfg

Thank you,

Paula

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The value returned by RMAN_assignResources function is IRES_ENORESOURCE...