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Memory related query

gorge ss
Prodigy 160 points

Other Parts Discussed in Thread: OMAPL138, OMAP-L138, TMS320C6748

Hi Experts,

I have some issues with the shared memory between the ARM-DSP subsystems (Omap L138 ). 

Psuedo code of my problem.

---------------------------------------
ARM side
-------------------------

#define ARM_UPDATED_MEM    (volatile int *)0x80000040

void armTsk (void)

{

  *ARM_UPDATED_MEM    = 0x1;

interruptDsp();

}

------------------------

DSP Subsystem

---------------------------

void DspISR (void)

{

 if(  *ARM_UPDATED_MEM == 1)

  LOG_printf("&trace, "Arm has signalled mem updation\n")

}

After the Arm has updated the shared memory it signals an interrupt to the DSP and in the DSP ISR it checks the status of the updated memory by reading the same memory location updated by the ARM. Though the arm has updated the memory,  when Dsp reads the memory inside the ISR, it doesn not match with 0x1 ie it does not get updated. But from the memory dump on the dsp side, it shows that the value is 1.

I think this could be due to some cache issue, I dont know how to solve this problem, Can any one kindly guide me on how to flush the cache which i feel is the actual problem.

Thanks in advance.

gs.

  • 0
    Guru 31670 points

    GS,

    This is a simple problem of cache. You have to flush the cache at ARM side and invalidate the cache location at DSP side if you are caching at DSP too. 

    Simple method to solve is to use un-cached area in memory for the same.

  • 0 in reply to Renjith Thomas
    Prodigy 160 points

    But how to do that, any sample code ??

    Also do i have to invalidate in the ISR ?

    how to select an uncached memory, or if i want to make this memory as uncached what are the steps.

    Plz guide.

    gs

  • 0 in reply to gorge ss
    TI__Guru** 116830 points

    GS,

    Cache  related APIs and sample code can be found in OMAPL138 Starterware package. If this is an non-OS based application you may want to take a look at this package for multiple reasons. Apart from cache related APIs, it also contains a package called IPClite and some examples associated with it that show the inter-processor communication

    http://processors.wiki.ti.com/index.php/StarterWare

    Hope this helps.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 160 points

    Thanks,

    Could anyone please quide me how to make the memory for example (0x80000040 - len 0x200) as uncached. this will solve all my issues.

  • 0 in reply to gorge ss
    Guru 31670 points

    Gorge,

    Are you using Linux on ARM side? If you are using Linux, you can use the API ioremap in Linux to get uncached virtual address. If you use this address, the memory will not be cached.

    Or else, if you still want to use cached memory, you can selectively do a cache_range_flush which will result in flushing the portion of cache. I'm not sure about the API though

  • 0 in reply to Renjith Thomas
    Prodigy 160 points

    I just need to know in terms of h/w registers wht setting do i need to program to make a specific memory for instance address 0x80000000 (again  its a hard coded memory not any dynamically allocated one) into uncached memory. I am not using any OS. 

    And more over i think it is possible to make it uncached from DSP subsystem aswell, but any pointers would be highly appreciated. (Note: i have already referred to starterware and its of not much use to me).

  • 0 in reply to gorge ss
    Prodigy 170 points

    For the DSP side on the OMAP-L138, I found the following documents helpful:

    sprufk5 - TMS320C674x DSP Megamodule, Sections 2.6, 3.4, and 4.4 have the actual registers and addresses

    sprug82 - TMS320C674x DSP Cache User's Guide, Section 2.3 contains a description of what registers you may need to configure for memory.  

    sprugj7 - TMS320C6748 DSP System Reference Guide - the related documentation contains references to the above two documents.  It gives general overviews of cache use and connections throughout, and provides the sizes of each of the memories.

    Unfortunately, I cannot speak personally for setting cache sections, since on our application, we turned all caching off.  I think "external" here referrs to "external to the DSP" since this is a DSP specific document, so the shared RAM address you are using should fall into this category.  However, the DSP should not cache external memory by default after a reset (spruga82a, Sec2.3), so I may have this incorrect.  This may actually mean using external memory space as a cache.  I don't know.  Hopefully this helps you get started looking.