Hello,
We are planning to use the OMAPL138 and a Xilinx FPGA in our system. The plan is to use the FPGA to de-serialize a handful of serial ports, and transfer that data to the OMAP in a parallel fashion. We are considering using the uPP port, but have a few questions on the uPP interface and the software involved with it.
1) When using the uPP interface, is the TX Clock signal always active once OMAP is operational? (– e.g., can we use it as an input clock to run other FPGA logic. )
2) There is brief mention of a FIFO scenario that can be used with the uPP.
a. Can the FIFO be used on the tx and rx sides of the uPP?
b. For DSP receive side - How would software interact with this fifo – e.g., which Interrupt bit would be used to tell software that data was in the fifo?
c. Also, if the DSP fifo is full, will he uPP wait signal automatically be asserted to throttle the FPGA and prevent an over-run?
d. For DSP transmit side – software could write data to the uPP tx fifo, but how does it know when to start transmitting the fifo contents to the FPGA over the uPP bus?
e. How does SW read/write to the FIFOs, does it have to setup a DMA engine to transfer to/from the FIFO’s?
f. Is there any more documentation on the FIFO feature besides the brief paragraph in the uPP User Guide?
Sorry for the 20 questions, but I wasn't able to find this detail in the documentation, and I need some help with how the software works on this port.
Thanks!
