Hi:
I am using 8bit nand, SLC, 2KB/PAGE.
We are ready to flash the nand using flasher , how to generate OOB data for every page(2048Bytes) without dm8148.
The ecc mode we used is BCH8.
Thanks!
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Hi:
I am using 8bit nand, SLC, 2KB/PAGE.
We are ready to flash the nand using flasher , how to generate OOB data for every page(2048Bytes) without dm8148.
The ecc mode we used is BCH8.
Thanks!
Peng,
Which is the programmer that you are going to use? Have you checked out http://www.bpmmicro.com/4800.html?
Hi Renjith Thomas:
We already have flash programmer in our factory now, and our factory need the (PAGE+OOB) image only.
So, we must make a tool that convert our data image ( only data) to factory image ( data + oob, aligned).
Thanks.
Peng,
If you just need a the data only, then you can write a simple C application to write all the images to a file based on the NAND offset. If everything follows the same ECC algorithm it will be really simple.
Alternatively does your programmer can read from a reference NAND flash? If so, flash the entire production image and give programmer as input.
Hi Renjith Thomas:
Our flash programmer can not generate bch8 ecc code ! It just write the raw data page(2048+64) by page.
So, i must get BCH8 ecc algorithm and write a application to generate the image with oob data, such as this function:
int gen_bch8_code(unsigned char *data_buffer, unsigned char *oob_buffer, int len)
{
}
by the way, use a nand flash as input is not acceptable .
Hi Peng,
I'm not really sure about the availability of code for BCH8 encoding. But you can have a look at the file in Linux kernel path drivers/mtd/nand/omap_bch_decoder.c where BCH8 decoder is implemented. You can use this as a starting point.
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
u8 res2[0x4];
u32 irqstatus; /* 0x18 */
u32 irqenable; /* 0x1C */
u8 res3[0x20];
u32 timeout_control; /* 0x40 */
u8 res4[0xC];
u32 config; /* 0x50 */
u32 status; /* 0x54 */
u8 res5[0x8]; /* 0x58 */
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
u8 res6[0x14]; /* 0x1E0 */
u32 ecc_config; /* 0x1F4 */
u32 ecc_control; /* 0x1F8 */
u32 ecc_size_config; /* 0x1FC */
u32 ecc1_result; /* 0x200 */
u32 ecc2_result; /* 0x204 */
u32 ecc3_result; /* 0x208 */
u32 ecc4_result; /* 0x20C */
u32 ecc5_result; /* 0x210 */
u32 ecc6_result; /* 0x214 */
u32 ecc7_result; /* 0x218 */
u32 ecc8_result; /* 0x21C */
u32 ecc9_result; /* 0x220 */
u8 res7[12]; /* 0x224 */
u32 testmomde_ctrl; /* 0x230 */
u8 res8[12]; /* 0x234 */
struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
};
In a word, the ecc result of BCH8 is generated by gpmc now, and we want to generate it by our self.
BCH8 algorithm is implemented in hardware inside GPMC. But how will we implement the same in software?
Can you tell me where you found the BCH ECC code please? I have the same problem.
Steve.
Steve,
What exactly are you trying? Can you give details of your problems with logs?
Renjith,
I am trying to pre-program NAND flash chips in production. The data is just the binary (uBoot, etc.), but the DM8148 GPMC expects that the spare area of each page contains the ECC codes. We have tried booting without the ECC programmed and no code is copied to SRAM. From the information that I have found it seems that the ROM boot loader uses 8bit BCH encoding for the ECC. Is this correct? It also seems that the ECC data is stored in the spare area of each page in a format specified in the TRM (sprugz8a Figure 4-15). Is this correct? So to pre-program NAND flash it seems all that I need is to know what the 8bit BCH algorithm is. Can you provide details of the algorithm?
Thanks.
Steve.
We'd be interested in try such a solution for BCH16 too, as a workaround - the DM814x EZSDK doesn't support writing an image with BCH16, even though the ROM loader requires it when NAND parts with large enough spare area is used!
Steve,
Steve Mellor said:From the information that I have found it seems that the ROM boot loader uses 8bit BCH encoding for the ECC. Is this correct?
Your understanding is correct
Steve Mellor said:It also seems that the ECC data is stored in the spare area of each page in a format specified in the TRM (sprugz8a Figure 4-15). Is this correct?
True.
Steve Mellor said:So to pre-program NAND flash it seems all that I need is to know what the 8bit BCH algorithm is. Can you provide details of the algorithm?
BCH 4,8,16-bit algorithm is implemented in hardware inside the GPMC NAND controller. Refer the device's Technical Reference Manual for complete details.
Hi Steve:
we got some useful code from linux kernel: \linux-3.3.4\drivers\mtd\nand\nand_bch.c
Hope it helps you .
I can find a description of how the BCH algorithm is used and the results stored in the spare area (sprugz8a Section 11.2.4.12.3.2), but not of the algorithm itself. I will try to algorithm in the Linux kernel and see if that works.
Steve.