Hello!
I beg for your help in understanding the DM355 AEMIF memory map. First of all, I'll begin with the actual problem, which caused me to dig on the subject deeply. I work with custom DM355-board, which has a 1Gb NAND chip and the JTAG, as the only outer interface. All software is already written and tested on the DVEVM board. So the only problem is to flash it to the NAND chip. I've flashed the DVEVM board with OpenOCD via JTAG successfully, but when I've tried to do the same with custom target board, I've faced the problem.
As I've already said, the custom board has the 1Gb (8GBx8) NAND chip, which has a single NAND bank and so the only CS input. When I've launched OpenOCD with original initialization scripts, if found two NAND banks (as written in the script for DVEVM board), who mirrored each other. And the worst is, that they are acessible for reading only. When I try to erase or write data into NAND, OpenOCD gives successful messages, but data in NAND remains the same.
So I thought, that the problenm may be in NAND initialization scripts and tried to understand them. And so appeared my questions, which I beg you to andswer.
1. The DVEVM Techincal Reference paper tells, that DM355DVEVM AEMIF has two chip enable spaces, which are located in 0x02000000 and 0x04000000 respectively. And, at the same time, it has chip select spaces, which are located in 0x02000000 and 0x02004000 respectively. I can not understand, how the one agrees with the other. Does each of the chip enable spaces divided into two chip select spaces? Or both chip enable spaces address range are divided in two chip select spaces?
2. The memory map in sprs463g.pdf has no division into chip select and enable spaces. It has the only ASYNC EMIF data slot beginning in 0x2000000 and ending in 0x09ffffff. Is the chip enable and select spaces division the feature of the DVEVM? Could it be somehow altered?
3. As far as I could understand from papers first chip enable (or chip select?) space matches to NAND chip drived by EM_CE0 signal, and the second - by EM_CE1. But in DVEVM schematics only the EM_CE0 signal is used to drive the dual-chip NAND flash with two CS inputs. And the EM_CE1 drives the ethernet controller. How the existence of two chip select (or enable?) spaces agrees with the single EM_CE0 signal, driven to NAND memory.
Thank you in advance