Paragraph 5.4.1.2 (page 108) in the DM365 Video Processing Front End (VPFE) User Guide (SPRUFG8C) states:
"Prior to enabling the ISIF, the hardware must be properly configured via register writes. Table 5-1 identifies the register parameters that must be programmed before enabling the ISIF. Since many of these registers are latched into the hardware by the PCLK, it should be actively clocking during register configuration."
Can you please confirm if the PCLK *must* be clocked during register configuration? The problem for us is that we're trying a camera sensor that powers up in a low power mode and it only enables its output PCLK when told to via I2C. When the DM365 powers up it loads the VPFE driver first and then the camera driver. PCLK isn't active until the camera is actually used for the first time. Unfortunately the DSP will wait indefinitely for the video even though the camera output stream is active. I'm trying to get the camera to output its PCLK sooner during boot but it's not trivial. Any help you can provide would be appreciated.
