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Chip Select (SPIx_SCSn) Utilization with the OMAP-L138 SPI Port (SPIx)

Steve Maltrud
Prodigy 250 points
Other Parts Discussed in Thread: OMAP-L138

 

Re: the OMAP-L138 SoC:  There are 2x SPI ports and up to 8x SPI Chip Selects (SPIx_SCS[0:7]) available for use.  Is it possible to utilize two or more CS’s within a single SPI port to have the capability of communicating individually with more than one SPI peripheral chip on the SPI bus?  The UG and DS info seems to not address this capability.  If it can be done, what are the limitations of doing so?  Please see above attached image for proposed schematic.

 

  • 0
    TI__Expert 5740 points

    Hi Steve,

    Yes, tying multiple slave devices on one SPI port via multiple CS lines is a typical way of connecting multiple devices.

    Your diagram does have a small error, your SOMI (MISO) and SIMO (MOSI) lines appear to be switched. SOMI (slave-out master-in) should direct into the OMAP master, and SIMO (slave-in master-out) should direct into the slave devices.

    One limitation with this type of configuration is that all slave devices will need to have tri-state outputs on their SOMI lines, so that when their corresponding CS is not asserted the output is high-impedance.

     

    Let me know if that answers your question,

    Keegan

  • 0 in reply to Keegan@TI
    Prodigy 250 points

    Keega,

     

    You are correct.  I actually caught it about 2 sec after i posted it.  But I didn't want to clutter the post.  I got the answer in needed.  Do you know of any example code for this multi-CS operation?

  • 0 in reply to Steve Maltrud
    Prodigy 10 points

    Hi Keegan, Steve,

    With multiple slave devices (as depicted in your drawing above). When cs[k] of device k is activated (goes low), transaction completes and cs[k] is automatically deactivates (goes high). For the k+1 device to be engaged in a transaction, it is necessary for the CPU to set SPIDAT1.CSNR[k+1] to low. Is there another way to activate device k+1 without CPU intervention?

    BR, Yaniv