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DM8148 - XIP (on GPMC) Boot Options

YILMAZ KIRÇİÇEK
Intellectual 905 points

Hi All,

I have seen that  (J28,K27,....) pins have been used for GPMC_A[1:12] signals on Mistral DM8148 board. This means designer has selected M1 option according to Table 4-2 on SPRS647D  (page 153/54)

So I expected that M1 option pins should be used for  GPMC_A[20:23] signals.(Please see PINCNTL113...116)  But M0 options have been used for GPMC_A[20:23] signal on Mistral DM8148 board. I do not have a Mistral DM8148 board to test but I am sure any one has tested that if NOR Flash working properly for XIP boot.

Is there a simple point that I can not able to see or is there a confiliction between Table 4-2 on SPRS647D and Mistral DM8148 board schematics?

GPMC_A[20]            (M0)                  AD28 
GPMC_A[21]           (M0)                   AC28 
GPMC_A[22]           (M0)                   AB27 
GPMC_A[23]           (M0)                   AA26 

GPMC_A[24]/GPMC_A[20]              L25
GPMC_A[25]/GPMC_A[21]              N23
GPMC_A[26]/GPMC_A[22]              P22
GPMC_A[27]/GPMC_A[23]              R24

Best regards.

  • 0
    TI__Guru**** 393215 points
    Hi Yilmaz,
     
    Currently XIP boot is not supported on the DM814X EVM. Other than that, the NOR flash located on the I/O expansion daugtherboard is usable.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    Intellectual 905 points

    Hi Biser,

    My question was about NOR flash located on I/O expansion board.

    If you fallow the signal A[20..23] from the rest of the schematic, you will see that these come from AD28, AC28, AB27, AA26 pins of DM8418. That shows us designer has selected Mux0 option for these signals.

    And also you can see that  (J28,K27,....) pins have been used for GPMC_A[1:12] signals on Mistral DM8148board. This means designer has selected M1 option according to Table 4-2 on SPRS647D  (page 153/54)

    Some of the address signals is selected for Mux1 and  the others comes from Mux0.  As I know BTMODE[4:0] is used to select only one of Mux0 or Mux1.

    Could you please look a little bit closer to firt post.

    So what is the point that I am missing or is there a confiliction between Table 4-2 on SPRS647D and Mistral schematics ?

  • 0 in reply to YILMAZ KIRÇİÇEK
    TI__Guru**** 393215 points
    Hi Yilmaz,
     
    MUX0 and MUX1 are relevant only to booting from NOR. As I said, this option is not supported on the Mistral board. So, these pins can be freely pinmuxed in the bootlader or kernel to use the NOR flash after boot. Otherwise your observations are correct, and this is the reason that XIP booting is not supported.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    Intellectual 905 points

    Hi Again,

    Thank you very much for your answer. 

    Asking to be sure; I can still boot  from NOR flash with XIP unless my code does not exceed A[0..19]. After boot I can access entire NOR flash by modifying PINCNTL registers. (Higher address bit should be set 0 during boot )

    And also did any one inform Mistral about this issue, because their document is still not claim to support XIP boot. (They do not respond directly to me)

  • 0 in reply to YILMAZ KIRÇİÇEK
    TI__Guru**** 393215 points

    Yes, practically this is the solution. You have to modify your bootloader so that the first portion which can be accessed at boot time enables the whole NOR flash. If you search this forum for "XIP boot" you'll find a couple of posts that address this.

    BR
    Biser
  • 0 in reply to Biser Gatchev-XID
    Intellectual 905 points

    Thank you for all,

    Best Regards.