Wrong data in AIF transfer

your explanation doesn't make sense to me. you said you could see the correct data on receiving DSP. how you could check this? put a break point somewhere and read memory map? and then you could see all 0xFFFFFFFF data when you "STOP" the test. what do you means when you say "STOP"?

Albert

The program is tested between DSP1 on TMS320C6474 EVM1 and DSP2 on TMS320C6474 EVM2 with SMA connecting, and the used link is, of course, link 0.

Here is my code for receiver(once it received enough frames and the last data is correct, it stops):

if(0x000006FF==antennaBuffer[0].uiInboundAntennaPingBuf[6][255]&&FsyncEventCount[1]==100)
{

 for(i=0;i<7;i++)
  {
 for(j=0;j<256;j++)
  {
  result[i*256+j] = antennaBuffer[0].uiInboundAntennaPingBuf[i][j];
  }
 }

asm( " .long 0x1001E000" ); //software breakpoint

}

After the program reached the software break point, I check the memory map,the data in result[] are correct but data in antennaBuffer[0].uiInboundAntennaPingBuf[][] are all 0xFFFFFFFF. It seems that the data in antennaBuffer[0].uiInboundAntennaPingBuf[][] have changed before the software point. Then I add a piece of code to reset aif module,edma module and fysnc module, the code changed to:

if(0x000006FF==antennaBuffer[0].uiInboundAntennaPingBuf[6][255]&&FsyncEventCount[1]==100)
{

DoCleanup();

 for(i=0;i<7;i++)
  {
 for(j=0;j<256;j++)
  {
  result[i*256+j] = antennaBuffer[0].uiInboundAntennaPingBuf[i][j];
  }
 }

Then I check the memory map, the data in both result[] and antennaBuffer[0].uiInboundAntennaPingBuf[][] are all correct, what's the possible problem?

(the same code between two DSPs on the same TMS320C6474 EVM does not have this problem)

I think it is related to synchronization between two DSP on different board. if we have two DSPs on the same board, we share clock, frame sync and there is no timing problem. but separate board can cause this kind of trouble because we can not make perfect equal timing when we shut down AIF on each board. so certain pattern of garbage data can be transferred to the memory while one DSP is running and the other one is trying to shut down. are you sharing ref clock and timer0 output sync signal between two boards?

albert 

Thanks for your answer! Yes, I use wire to connect JP8 on two TMS320C6474, so timer0 of DSP1 on EVM1 could trigger fsync on EVM2. Is there any possible solution of this problem?

Thanks for your answer and I'll see what I can do.

Hi, sorry to bother you again. But I am wondering how can I share AIF reference clock between two TMS320C6474?

Use TI Break out card for the EVMs. TI BOC has its own clock generator on the board and share that clock for both EVMs.

You may get more info about BOC from TI marketing or any other TI support person.

Albert