EVM SRIO SerDes multiplicator values

Alberto Chessa

Hi,

I'm experimenting with the SRIO on the EVM using as base the example in PDK.

In the deive configuration (device_srio_loopback.c), the SERDES seems to be programmed for 5Gbps, but the used SERDES MPY value is not present in the MPY table in sprugw1a Serail Sapid IO user manual, §2.3.1.1.

The example code set SERDES_CFG_PLL to 0x235, that is MPY=0b11010, and RX/TX CFG RATE=half.

Since the EVM clock is 312.5, looking at sprugw1a table 2-7, 5Gbps need MPY=8=0b00100000, that don't match the configuration of the example.

Somebody know what MPY = 0b11010 means and where is the complete list of the MPY multiplicator values?

I tried to set MPY=8, but the SERDES don't lock, while with the exapmle configuration it works.

over 12 years ago

0 Elush Shirazpour over 12 years ago

TI__Intellectual 2790 points

Hello Alberto,

Can you tell me which PDK you are using? PDK_6678, PDK_6670, PDK_6657?

Thank you

Elush Shirazpour

0 Alberto Chessa over 12 years ago in reply to Elush Shirazpour

Mastermind 6670 points

I'm using pdk_C6678_1_0_0_12 on EVM TMX320C6678LE rev.1.0.

During my test a made a mistake when configuring MPY=8 (0b00100000). Now it works with 8x also,that is ERDES_CFG_PLL=0x241

Anyway it works also with 0x235, but, at what is the speed?

In revision A of the SRIO User Guide (sprug1a) the formula in "Table 2-5 Line Rate Versus PLL Output Clock Frequency" has been removed, but "Table 2-7 Frequency Range versus MPY Value" it seems that:

SRIO_GBPS = RefClk * MPY * RATESCALE

On the EVM: 5Gbps = 312.5MHz * 8 * 2

So If, on a custom board, the RefClk is, for instance, 200Mhz (on the SRIO_SGMII_CLK input of the C6678) and I want to go at 2.5Gbps, I have to set MPY=12.5 and RATESCALE=1 (quarter). Is it correct?

0 Elush Shirazpour over 12 years ago in reply to Alberto Chessa

TI__Intellectual 2790 points

Alberto,

The "Table 2-5 Line Rate Versus PLL Output Clock Frequency" has not been removed from the SRIO User Guide. You can find it here, http://www.ti.com/lit/ug/sprugw1a/sprugw1a.pdf

In your example, you have 5Gbps = 312.5MHz * 8 * 2 but according to "Table 2-7 Frequency Range versus MPY Value", its that RIO ref clock is 312.5 MHz, MPY is 8, and Line Rate is 5 Gbps at a half rate rate scale.

The following is the expression for calculating the MPY for a required line rate @ a particular RIO ref clock:

RIO ref clock = (LINERATE * RATESCALE) / MPY

RATESCALE = 0.25 (full rate), 0.5 (Half rate), 1 (Quarter rate) and 2 (Eighth)

The C6678 does not support 200MHz as an SRIO reference clock. The only supported frequencies are 156.25MHz, 250MHz and 312.5MHz. We can not guarantee the operation of the SRIO across process and temperature unless a clock is used which meets the jitter specifications and is one of the specified frequencies.

If I have anwsered your question, please click the Verify Answer button on the bottom of this post.

0 Alberto Chessa over 12 years ago in reply to Elush Shirazpour

Mastermind 6670 points

Elush Shirazpour said:

The "Table 2-5 Line Rate Versus PLL Output Clock Frequency" has not been removed from the SRIO User Guide.

The table is present, it is only the formula that has been removed (RIOCLKFREQ = (LINERATE x RATESCALE)/MPY).

In table 2-4, row MPY, the description say PLL multiply. Select PLL multiply factors between 4 and 60, but in the values list only some values are present and, for instance, 60 is missed. The MPY encoding appers to be "non linear".

0 Elush Shirazpour over 12 years ago in reply to Alberto Chessa

TI__Intellectual 2790 points

Alberto,

Ill have to check with the team to see if the SRIO User Guide really meant to say 4-25 or they did not just list out all possible MPY values.

For now, I believe it is that all the MPY values were not written out and I would use 11110000b to represent MPY as 60 for now.

Thanks

Elush Shirazpour

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EVM SRIO SerDes multiplicator values