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what does sysbios do for hardware initlialization

Other Parts Discussed in Thread: SYSBIOS

Hi there,

Is there any document describing what sysbios does for hardware initialization? Or can you help correct my following summary?

for c66x dsp platform, e.g. EVM6678 

- main PLL, however, is the main PLL workaround included?

- l1d, l1p, l2cache settings

- the timer for clocking usage

- any interrupt mapping if configured in HWI/ECM

NOT initialized by sysbios:

- DDR

- ECC

- MAR bits 

- srio, gemac, pa and etc. 

I just want to make this clear because I don't want to miss any hardware initialization for standalone running.

B.R.

River 

  • Hi,

    BIOS does not init the PLL for c66xx.  For some other devices like C28 we do do some PLL initialization.

    WE do init the MAR bits.

    I think those were the only two things I found incorrect from your initial post.

    Judah

  • Hi Judah,

    Thanks for the answer. Yes, I have just found  MAR bits are by default set if c64p cache module is added. Maybe my question is not a good question because it depends on whether any module is involved in the cfg file.

    However for main pll, I still think it is initialized by sysbios because cpu clock speed is set in platform edit/view. Could you help further clarify it? Thanks!

    B.R.

    River 

  • That's correct the MAR bits are set by the Cache Module.  I think its always brought in...not 100% sure about that.

    No, the cpu clock speed in the platform is simply for telling SYSBIOS what speed your board is running at.  BIOS will not actually go set it for you.  This needs to be done by a GEL file if using CCS or bootloader or some other method.

    Judah