Hi all,
I am looking at the eZDSP board with the 5505 DSP and I got a question on the actual clock speed that is used. The code I am running is the FFT filtering example from http://code.google.com/p/c5505-ezdsp/ and the board is the red eZDSP 5505, the box says rev C.
I have been changing the code a bit to try to get it to run faster (The default settings does not work, not enough time). I have changed the led to be on before an interesting section of the code, and off after it and I use an oscilloscope to measure the actual time spent on that code. I changed the frequency domain multiplication with the complex multiplication implemented in assembly from SPRU376A, example B-14. Huge speed improvement.
I have tried using both of the 5505 eZDSP configs available in my installation of CCS4 (the one that came with the board).
My observations are as follows:
On entering debug mode it says it inits the PLL to 100 MHz.
The FFT part is too slow to use the hardware or the clockspeed is not 100 MHz. The time spend on a 1024pt fft is ~3.9 time too long so either the clock is about 25MHz or the FFT hardware is not used (ref FFT benchmarks in SPRABB6A)
Inserting 12 NOP inside the localrepeat from example B-14 (see above) increased the time for one loop from 125us to 600 us, or 47500 cycles@100MHz. This translates to 3.8656 cycles per NOP but it should take one cycle.
My conclusion is that the DSP does not run at 100 MHz. I have tried to experiment with the PLL settings to see if I can confirm this, but nothing seem to affect the execution time. Changing the gel file gives another console output (ie. Configuring PLL (40.00 MHz) instead of 100MHz) but execution speed is still the same. The scripts menu is never available so the proposed method from the CSL examples documentation (http://software-dl.ti.com/dsps/dsps_public_sw/dsps_swops_houston/C55X/latest/exports/C55XCSL-LOWPOWER-3.00.00.02_Release_Notes.pdf page 18) does not seem to be working in my case.
Any hints will be very appreciated.
Best regards,
Jakob
