C6474 bootloader PLL mode?

Michael P

Table 31 in SPRUEC6G says "For all bootmodes, the PLL is set to x16 mode." This does not correspond with what I see on a silicon revision 2.1 DSP (DEVID.VARIANT=4).

If I connect an emulator to a DSP using boot mode 9 (DEVSTAT register value 0x00000022), trigger a warm reset for the DSP, and let the bootloader run for a while -- with no SRIO transactions being sent to the DSP -- I see the PLL1 registers stay in their reset values (PLLCTL.PLLEN=0, PLLM.PLLM=0, and so forth).

Is this the expected behavior? Is the application responsible for programming the PLL, even if it wants x16 mode?

over 13 years ago

0 Chad Courtney over 13 years ago

TI__Mastermind 30825 points

Did you check the RESETSTATz pin before doing this? Are you 100% certain you're looking at PLL1 control registers - Pull them up in a memory window and check the PLL1 values.

Best Regards,
Chad

0 Michael P over 13 years ago in reply to Chad Courtney

Expert 1810 points

RESETSTAT# reads deasserted, and when I pause the bootloader's execution to check the PLL1 control registers, the program counter is at 0x3C001364 -- I am pretty sure the DSP is no longer in reset. If I look at memory starting at 0x029A0000 in a memory window, I see these values:

0x029A0100 (PLLCTL): 0x00000048 (PLLRST=1, PLLEN=0)

0x029A0110 (PLLM): 0x00000000

0x029A0114 (PREDIV): 0x00000000

0x029A0150 (SYSTAT): 0x00003FC0

0 Chad Courtney over 13 years ago in reply to Michael P

TI__Mastermind 30825 points

I'll have someone who works on the RBL code take a look at this and comment.

Best Regards,

Chad

0 Michael P over 12 years ago in reply to Chad Courtney

Expert 1810 points

Any update on this question? It touches on a separate problem that I am seeing -- although I think my code sets up the PLL correctly (as described in SPRUG09 and the C6474's data manual), I would rather touch as few of these registers as possible, in order to narrow down the potential causes of the other problem.

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C6474 bootloader PLL mode?