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Can EDMA be used to control GPIO state?

Other Parts Discussed in Thread: ADS8332

Hello

I have a C6747 design where I am using two TI ADS8332 a/d converters in daisy chain cfg to SPI port 1. In this cfg the CS requires special handling, i.e. it must be low continuously through spi read of both parts but then must go high between a/d conversion cycles. This is easily handled using a GPIO when running in interrupt-driven mode where the processor is interrupted for every adc conversion cycle and the port read under ISR control. However, a friend has advised me that I will have much better performance using EDMA to transfer the data for each conversion, and then interrupt the processor after certain number of conversions, say 512 or 1024. In this mode I would not have any ISR code to control the gpio for each conversion, it would have to be automated somehow in the edma. I am wondering if it is possible to implement the following chained edma sequence for each conversion:

external trigger to start --> edma writes value to gpio out register to set CS gpio low --> chained edma services spi port --> chained edma writes value to gpio out to set CS high --> cycle complete, wait for next external trigger and repeat

The main thing I am unsure of is whether it is a valid operation to write to the gpio control register using the edma. Any suggestions are appreciated.

Thanks,

Steve

  • Steve,

    Yes, it is a valid operation to write to the gpio control register using the edma.

    In the datasheet is a Memory Map Summary that shows the address ranges that can be accessed by the several bus masters in the device. Under the EDMA heading, you will find the address range for GPIO included. This is how you know that this region of addresses can be accessed.

    On some of our devices, there is a System Interconnect table that you can look at to determine which regions or peripherals are available to the different masters. This is not part of the C6747 architecture, though.

    Regards,
    RandyP