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DM8148 Cache configuration

dohan tang
Prodigy 60 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

My platform is DM8148+SysBios, it is multi-core platform.

I want to config code area is I-Cached only, data area is D-Cached only, and some memory space is non-cached.

How to do the configuration in Sysbios environment? 

  • 0
    TI__Mastermind 32475 points

    What version of SYSBIOS are you using and which processor you are trying to configure for?

    Judah

  • 0 in reply to judahvang
    Prodigy 60 points

    Dear Judahvang,

    Thank you or your response.

    My Sysbios version is V6 (6.32.0.54).

    The platform is DM8148 it is a multi-core processor.

    I want some shared areas are non-cached, so all cores( Cortex-A8, Cortex-M3 and C674x) need be configured.

    Thank you

  • 0 in reply to dohan tang
    TI__Mastermind 32475 points

    Hi,

    Your SYSBIOS version is an older version so I don't know how much of what I'm saying is actually supported for that version.  If possible, it might make sense to move to a later version in 6.33.

    All those cores have different cache modules in SYSBIOS.

    A8 - ti/sysbios/family/arm/a8/Cache, ti/sysbios/family/arm/a8/Mmu

    M3 - ti/sysbios/hal/unicache, ti/sysbios/hal/ammu/AMMU

    C674x - ti/sysbios/family/c64p/Cache

    Each cache module does have some cdoc documentation associated with them.  I would go here first for information.

    I am most familiar with the C674x core, somewhat familiar with the A8, and not very familiar with the M3.

    I can tell you that for the C674x, you can use MAR bits to configure each 16MB of external memory, whether you want it cacheable or not.

    I believe the A8 uses an MMU which allows you to do something very similar.  I'm not sure what the block size are though.

    The M3 also has a unicache module and an AMMU.  I don't know the specifics of what AMMU does.

    Judah